A design method of lithographic overlay marking

Abstract

A photolithographic overlay mark design method of the present invention relates to the technical field of integrated circuit technology application, including step S01, designing the overlay mark and its coordinates inside the exposure area, and the overlay mark in each exposure area is not less than 10 First, the coordinate design of the overlay mark evenly covers the entire exposure area; S02, design the measurement coordinate method inside the exposure area, and measure the coordinates through two design methods: the complementary point selection method and the comprehensive point selection method; S03, carry out the process on the wafer Expose, and screen the overlay error measurement model within the wafer range, and label all exposure areas in the horizontal and vertical directions in the wafer coordinate system; S04, analyze and calculate the overlay error data, and feed back to The automatic control system is used to automatically correct the parameters of the lithography equipment, which improves the flexibility of measurement and the reliability of data, and improves the accuracy of feedback correction and overlay error compensation.

Description

technical field [0001] The invention relates to the technical field of integrated circuit technology application, in particular to a method for designing a photolithographic overlay mark. Background technique [0002] In the field of integrated circuit technology, due to the extremely complex process, it is particularly important and difficult to ensure precise alignment between layers to have a very small overlay error. [0003] Integrated circuit engraving and feedback problems are important factors that plague device yield. According to the method of feedback correction, the problem of overlay error feedback is divided into overlay error correction within exposure patterns and overlay error correction between exposure patterns. The overlay error correction within the exposure pattern refers to the correction of the overlay error inside each exposure area. It is realized by measuring the overlay error at the edge and inside of each exposure field and using a linear or hig...

AI Technical Summary

Problems solved by technology

For example, lithography equipment manufacturers suggest that the second-order overlay error compensation algorithm requires no less than 8 exposure area data points; the third-order overlay error compensation algorithm requires no less than 12 exposure area data points, Therefore, from Figure 4 It can be seen that the existing overlay mark layout in the paper cannot meet the compensation needs of the actual lithography process

[0005] In addition, in the traditional process measurement process, the overlay mark measurement of different exposure areas in the wafer is often limited to Figure 4 5 data points shown, and using the linear overlay error compensation method

When the residual error after overlay error compensation is still outside the specified range value, the data will not be available for use with higher order error compensation algorithms

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