Double-phase coefficient adjustable analog multiplication calculation circuit for convolutional neural network

Abstract

The invention discloses a double-phase coefficient adjustable analog multiplication calculation circuit for a convolutional neural network, and belongs to the technical field of calculation, reckoningand counting. The multiplication calculation circuit comprises a current type network digital-to-analog conversion module, a double-phase coefficient adjustable analog multiplication array, a pipelined analog-to-digital conversion module and a calculation unit control module, a discrete time circuit structure is adopted to achieve multiplication calculation of a neural network layer, signed multiplier design is newly added to provide forward control and negative control, multiplication with sign bits can be achieved, and voltage amplitude in a wider range is provided.

Description

technical field [0001] The invention discloses a convolutional neural network-oriented dual-phase coefficient adjustable analog multiplication calculation circuit, relates to digital-analog hybrid integrated circuit technology, and belongs to the technical field of calculation, calculation and counting. Background technique [0002] There are already many better optimized designs for the convolutional layers of today's convolutional neural networks, with significant effects in terms of power consumption, area, and energy efficiency. For example, methods such as quantization and compression are used in data storage to realize the binarization of convolutional neural networks; in computing circuits, exclusive NOR gates are used as approximate multipliers for convolution operations, etc. Therefore, the further optimized design of the convolutional layer in the field of reduced network layers and digital circuits has reached a bottleneck period. The convolutional neural network ...

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Problems solved by technology

[0003] In order to solve the problem that the further optimization design of the convolutional layer of the existing neural network has reached the bottleneck period, the present invention provides a neural network-oriented dual-phase coefficient adjustable analog multiplication circuit, which can convert the digital signal in the multiplication operation into For analog signals, the discrete-time circuit scheme is used to design the analog multiplication calculation circuit, which can reduce the calculation power consumption of the irregular network layer and achieve high linearity robustness. The design of the dual-phase coefficient switching circuit can widen the frequency response tuning range

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