Two-stage error correction coding method and system applied to storage system in satellite severe environment

A storage system and error correction coding technology, applied in the field of on-board reliable storage systems, can solve problems such as difficult to guarantee the reliability of on-orbit systems, multiple single event flips, multiple bit errors, etc., to reduce the probability of irreparable, The effect of ensuring safe operation and reducing impact

Active Publication Date: 2019-11-22
NANKAI UNIV
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  • Application Information

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Problems solved by technology

[0006] The present invention aims at the phenomenon that multiple single-particle flips occur when the on-board storage system is attacked by high-energy particles as the on-orbit spaceflight operation environment becomes more and more complex, causing There are multiple bit errors in the word, but the conventional Hamming error-correcting code is difficult to guarantee the reliability of the on-orbit system. A two-level redundant coding scheme and system based on combined coding is proposed.

Method used

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  • Two-stage error correction coding method and system applied to storage system in satellite severe environment
  • Two-stage error correction coding method and system applied to storage system in satellite severe environment
  • Two-stage error correction coding method and system applied to storage system in satellite severe environment

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Embodiment 1

[0045] for figure 1 The different characteristics of the memory in step S1 will be described with reference to specific examples.

[0046] For example, the program memory PROM, NOR_FLASH itself is a read-only memory, and it is not easy to be affected by single events in the harsh environment of the space, that is, the reliability is high, so the EDAC (39,32) code with low error correction can still be used in the word, Parity code or high error correction code is used between words. For the data memory NAND_FLASH and the running memory SRAM, which have low reliability and more write operations, high error correction codes such as BCH double error correction codes can be used within words, and parity codes can be used between words. In this way, reliability, cost, and performance can be balanced according to the characteristics of different storage devices.

[0047] In the present invention, the original storage coding scheme BCH(44,32) is used for intra-word coding, and the ...

Embodiment 2

[0073] In this example, we mainly analyze the computing performance of encoding, error detection and error correction for the two possible intra-word coding schemes EDAC(39,32) and BCH(44,32) and the newly proposed two-level redundancy scheme. The experimental results are reflected in the relevant calculation process of encoding, and the inputs are the generation matrix required for different encodings, the parity check matrix required for decoding and the mapping table of syndromes and error patterns, the corresponding information generated randomly, and the random generated information in each stripe. wrong location. Taking encoding and decoding 1GB of data as an example, the preliminary test results of encoding and computing efficiency in two modes of internal memory and external storage are as follows: figure 2 , image 3 , Figure 4 , Figure 5 Shown:

[0074] Depend on figure 2 , image 3 It can be seen that in the memory system, compared with the two-level redun...

Embodiment 3

[0079] The experimental part of Embodiment 2 mainly reflects the calculation results related to the encoding and decoding of the two-level redundancy scheme. In this embodiment, the two-level storage coding is applied to the codec simulation system mentioned above, and the situation of writing and updating single words by the system is described. Its input is the required encoding matrix and the updated stripe address. Still taking the two-level coding BCH(44,32) and XOR(8,7) as an example, the two-level redundant coding is applied to the external memory. The abscissa is the number of user write (update) requests, and the ordinate is the average time it takes for the storage system to complete the update of each request. The experimental results are as follows: Image 6 shown.

[0080] pass Image 6 It can be seen that the method of updating and delaying writing applied to the external memory system has obvious advantages compared with methods such as updating synchronously...

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Abstract

The invention provides a two-stage error correction coding method and system applied to a storage system in an on-satellite severe environment. The method and the system mainly aim at solving the problem that when the storage system is attacked by high-energy particles in a space irradiation environment, a plurality of single event upset errors occur in a storage unit. The method comprises the following steps: 1, selecting an intra-word and inter-word coding scheme according to the characteristics of an on-board memory; 2, performing intra-character coding on each character; 3, after intra-word codes are generated, performing inter-word coding; 4, performing intra-word error detection in the decoding operation to obtain a corresponding syndrome; and judging whether the code word has an error or not according to the obtained syndrome, and if so, carrying out an error correction process; 5, in the error correction process, firstly performing intra-word restoration, and if the restorationcannot be passed, entering an inter-word error correction stage; and 6, an inter-character error correction stage: reading other characters in the same group of stripes, performing error detection, error correction and intra-character recovery, and if the other characters in the same group can be correctly recovered, performing inter-character verification to recover error stripes.

Description

technical field [0001] The invention belongs to the technical field of on-board reliable storage systems in harsh space environments, and in particular relates to a two-level redundant coding scheme and system based on combined coding. Background technique [0002] In the harsh space environment (such as the earth's radiation belt, and the corresponding cosmic rays), there are a large number of high-energy particles. When these charged particles pass through the microelectronic devices in the aerospace system, electron-hole pairs may be generated in the sensitive area inside the device. After these charges are collected by the electrodes of the sensitive device, it will cause abnormal changes in the logic state of the device or damage the device. Since this effect is the result of the action of a single particle, it is called a single event effect or a single event. [0003] Single event effects are divided into single event flipping, single event blocking, single event bur...

Claims

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Application Information

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IPC IPC(8): G06F11/10
CPCG06F11/10
Inventor 王刚罗金飞赵帅兵齐维孔李鹏刘晓光
Owner NANKAI UNIV
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