ZYNQ FPGA chip, data processing method thereof and storage medium

Abstract

The invention provides a ZYNQ FPGA chip, a data processing method of the ZYNQ FPGA chip and a storage medium. A PS part configures the operation parameters of a PE in a PEA of a PL part, and enables the calculation of the PE to be started; the PEA determines a read command, a write command and the number of the write commands according to the operation parameters of the PE, and sends the read / write commands to the read / write command interfaces of a DMA controller respectively; the DMA controller starts a data reading process from an external storage device according to the reading command, andsends the read data to the PEA; the PEA performs calculation according to the read data, and writes a calculation result back to the DMA controller; the DMA controller transmits a calculation resultto an external storage device, and waits for transmission completion and sends an end mark signal corresponding to each write command back to the PEA; and after the PEA receives the end mark signals with the same number as the write commands, the PEA sends an interrupt to the PS part, so that the overall performance of processing a deep learning model is effectively improved.

Description

technical field [0001] Embodiments of the present invention relate to artificial intelligence technology, and in particular to a ZYNQ FPGA chip, a data processing method thereof, and a storage medium. Background technique [0002] With the continuous development of deep learning, deep learning models are gradually being applied in various aspects, such as cloud computing, edge computing, and so on. Taking edge computing as an example, in the current research on artificial intelligence, the amount of data to be processed by edge computing has increased dramatically, which has far exceeded the on-chip memory of the core processor chip of the terminal device, and requires the use of external storage devices for intermediate data processing. temporary cache. Therefore, how to efficiently deploy deep learning models on terminal devices with fewer resources and lower costs will be highly limited by the data communication efficiency between the core processor chip and external sto...

AI Technical Summary

Problems solved by technology

Data switching between the PS part and the PL part leads to frequent data interaction between the DDRs on both sides and takes up data transmission time, thus affecting the overall performance of the deep learning model.

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