Comparator and analog-to-digital converter

Abstract

The invention provides a comparator and an analog-to-digital converter, the comparator introduces a load capacitance adjusting unit composed of a switch, a capacitor and a switch control logic on the basis of a traditional pre-amplification stage, the circuit structure is very simple, and the overhead of circuit design cannot be obviously increased; when the comparator is in a noise sensitive area, the switch is switched on to enable the capacitor to be connected to the drain electrode of the pre-amplification stage tail current tube, so that the time of the input tube working in a saturation area is increased under the condition that the bandwidth of the pre-amplification stage is not reduced, the noise of the comparator is reduced, and the precision of the comparator is improved; when the comparator is in a noise insensitive area or a reset stage, the switch is turned off to enable the capacitor and the drain electrode of the pre-amplification stage tail current tube to be disconnected, so that the speed of the comparator is further increased; meanwhile, a gain bootstrap unit is also introduced, a positive feedback structure is formed, and the gain of the pre-amplification stage and the speed of the comparator are increased; and based on the structural design, the static power consumption and the clock design difficulty of the whole latch are reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a comparator and an analog-to-digital converter. Background technique [0002] In recent years, with the continuous development of integrated circuit manufacturing technology, the feature size of CMOS devices has been continuously reduced, and the operating voltage of integrated circuits has also been continuously reduced. Under the deep submicron process, the working speed of analog-to-digital converters has been greatly improved. Improve, at the same time, power consumption is further reduced. However, as the core component of the analog-to-digital converter, the performance of the comparator has become a bottleneck in the design of high-speed and low-power consumption. Several traditional comparator structures are difficult to meet the requirements of speed, power consumption and low power supply voltage at the same time. [0003] In the case of low precision req...

AI Technical Summary

Problems solved by technology

However, as the core component of the analog-to-digital converter, the performance of the comparator has become a bottleneck for high-speed and low-power designs

Several traditional comparator structures are difficult to meet the requirements of speed, power consumption and low power supply voltage at the same time

[0003] In the case of low precision requirements, a single-stage latch structure can be used as the comparator structure. The advantages of the single-stage latch structure are fast speed and low power consumption, but its disadvantages are large noise and offset; In higher occasions, in order to suppress the high noise and high offset disadvantages of the single-stage latch structure, the comparator usually adopts a structure in which multi-stage pre-amplification stages are cascaded and then connected to the latch. Most of the noise is to increase the load capacitance of its pre-amplification stage, but the existence of the load capacitance of the pre-amplification stage will reduce its reset speed and increase its power consumption

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