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Polishing process for high-flatness 8-inch silicon wafer

A flatness and surface flatness technology, which is applied in the polishing process of 8-inch silicon wafers with high flatness, can solve the problem of low flatness in the polishing process, and achieve balance between mechanical and chemical effects, increase pressure, and increase rotational speed. Effect

Inactive Publication Date: 2019-09-27
TIANJIN ZHONGHUAN ADVANCED MATERIAL TECH
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  • Abstract
  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In view of this, the present invention aims to propose a polishing process for a high-flatness 8-inch silicon wafer to solve the problem that the flatness of the original polishing process is not high

Method used

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Examples

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Embodiment 1

[0016] Raw materials: 200 pieces of 8-inch lightly mixed sour rot;

[0017] Requirements: The thickness after polishing is 725±15, TTV requires 4 μm, TIR requires 3 μm, STIR (25*25) requires 0.5 μm;

[0018] Processing equipment: SPM-23 polishing machine, SCC pre-cleaning machine;

[0019] Measuring tool: ADE9600;

[0020] Accessories: polishing wax KW-20163, coarse polishing liquid 6504, medium polishing liquid and fine polishing liquid 3105, rough polishing pad SUBA800, medium polishing pad SUBA400, fine polishing pad 7355-000FE, wax remover, ammonia water, hydrogen peroxide;

[0021] Specific operation process:

[0022] The polishing process is wax polishing. Before polishing, the surface flatness value is tested, and then the surface of the silicon wafer is coated with polishing wax, and then the polishing wax is shaken evenly at high speed, and the polishing wax is baked at high temperature to make the wax have Sticky, and finally paste the side coated with polishing w...

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Abstract

The invention provides a polishing process for a high-flatness 8-inch silicon wafer. The polishing process comprises the following steps: step I, testing a surface flatness previous value of the silicon wafer, coating polishing wax on the surface of the silicon wafer, uniformly throwing the polishing wax, roasting the polishing wax for enabling the wax to have viscidity, pasting one surface coated with the polishing wax onto a high-temperature ceramic plate, and cooling the ceramic plate pasted with the silicon wafer; step II, performing rough polishing, intermediate polishing and fine polishing on the cooled ceramic plate to obtain bright flat silicon wafer; and step III, chipping off the silicon wafer obtained in step II, and performing ADE9600 to test the surface flatness. Mechanical action and chemical action are balanced by improving rough polishing process parameters in a polishing process, the surface flatness of the polished wafer is improved, and TTV, TIR, STIR and TAPER of a polished product can be reduced in comparison with an existing process.

Description

technical field [0001] The invention belongs to the technical field of silicon wafer polishing, and in particular relates to a polishing process for an 8-inch silicon wafer with high flatness. Background technique [0002] In the polishing process of silicon wafers, flatness is a very important parameter, and it is also a parameter that is difficult to optimize in the polishing process. The polishing of silicon wafers is to get a smooth and flat surface through chemical corrosion and mechanical grinding on the surface of silicon wafers etched by acid or alkali. With the reduction of semiconductor feature size and the improvement of integration, the requirements for the flatness of the silicon wafer surface are getting higher and higher, and the original polishing process cannot meet the higher flatness requirements. Contents of the invention [0003] In view of this, the present invention aims to propose a polishing process for a high-flatness 8-inch silicon wafer to solv...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B24B1/00
CPCB24B1/00
Inventor 王广勇金文明李星石明张琪韩鹏飞褚鑫王聚安吕莹孙晨光
Owner TIANJIN ZHONGHUAN ADVANCED MATERIAL TECH
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