High-heat-resistant packaging substrate

Abstract

The invention discloses a high-heat-resistant packaging substrate. The high-heat-resistant packaging substrate comprises a base plate, a circuit board, a high-heat-resistant insulating layer, a patterned conductive layer and an anti-welding layer, wherein the circuit board is positioned on the upper surface of the base plate; the high-heat-resistant insulating layer is arranged above the circuit board; the patterned conductive layer is arranged at the upper portion of the high-heat-resistant insulating layer; an electronic element is arranged in the patterned conductive layer; and a thermal expansion coefficient of the high-heat-resistant insulating layer is between the thermal expansion coefficients of the base plate and the electronic element. The thermal expansion coefficient difference among the electronic element, the high-heat-resistant insulating layer and the base plate of the high-heat-resistant packaging substrate is gradually reduced, so that the phenomena that the electronic element falls off and is stripped can be avoided, and the service life of the packaging substrate is prolonged; the high-heat-resistant insulating layer is adopted, so that the heat-resistant strength of the substrate can be improved; the thickness of the circuit board is small, so that the subsequently finished packaging structure has relatively small packaging thickness, and the heat dissipation efficiency of the packaging substrate is improved; and the packaging substrate is suitable for industrial large-scale production.

Description

technical field [0001] The invention relates to the technical field of packaging carrier boards, in particular to a high heat-resistant packaging carrier board. Background technique [0002] Chip packaging is to provide appropriate signal paths, heat conduction paths, and structural protection for the chip. The traditional wire bonding technology usually uses a lead frame as a chip carrier. As the contact density of the chip gradually increases, the lead frame can no longer provide a higher contact density. Therefore, a package carrier with a high contact density can be used instead, and the chip is packaged into the package through conductive media such as metal wires or bumps. carrier board. Usually, the core dielectric layer is used as the core material in the manufacture of the packaging substrate, and the multi-layer patterned circuit layer and the patterned dielectric layer are stacked alternately by using the full additive method, semi-additive method, subtractive m...

AI Technical Summary

Problems solved by technology

If the thickness of the core dielectric layer cannot be effectively reduced, it will inevitably cause a great obstacle in reducing the thickness of the packaging structure

[0003] In the existing packaging manufacturing process, due to the large difference between the thermal expansion coefficient of the chip and the packaging substrate, the chip cannot form a good bond with the packaging substrate, so that the chip or the bump located between the chip and the packaging substrate may automatically package glass on substrate

In addition, as the integration of integrated circuits increases, due to the thermal expansion coefficient mismatch between the chip and the packaging substrate and the insulating layer, the thermal stress and warpage caused by it are becoming more and more serious, resulting in the chip and packaging substrate drop in reliability

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