A clock tree trunk topology generation method and system capable of perceiving integrated circuit layout information

Abstract

The invention discloses a clock tree trunk topology generation method and system capable of perceiving integrated circuit layout information. The clock tree trunk topology generation method comprisesthe following implementation steps: dividing a full-chip layout into a plurality of grids; Finding out an obstacle position area in the full chip; Judging the position relation between the target point and the obstacle position area, and adhering or expanding the starting point and the end point coordinate point to grid intersection points near the obstacle boundary; Obtaining a shortest grid distribution channel between the target point and the terminal point; And inserting clock buffers into the channel with the shortest total step length according to a specified interval, searching an available placement position near an insertion point of the clock buffers to finish placement of the clock buffers, and finishing generation of clock tree trunks. Through path finding of the clock tree trunk of the core and protection of clock signal winding, the clock tree trunks of a plurality of clocks are created on the CPU chip, the coupling capacitance of other signals to clock signals is reducedto the minimum, the transmission quality of the clock signals is ensured, and the performance of the chip is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a clock tree trunk topology generation method and system for sensing integrated circuit layout information, which are used to generate a top-level clock tree trunk topology structure of a high-performance CPU. Background technique [0002] As we all know, there are multiple clock domains in high-performance CPUs. In order to make the clock signal output by the clock phase-locked loop (PLL) undisturbed and transmitted to each subsystem after a short delay, there are clock trees in the integrated circuit. The clock buffer of the clock transfers each clock to the subsystem clock entrance respectively. However, when the chip performs static timing analysis, the clock tree will be affected by the process, voltage and temperature, so that the clocks actually received by the two block circuits related to the timing are deviated, which affects the convergence of the sequential ci...

AI Technical Summary

Problems solved by technology

This type of method is inefficient. When the logic or design layout changes, the previous work will be repeated, which will affect the progress of the full-chip clock tree design.

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