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A high-speed grid driving unit and a circuit

A gate-driven, high-speed technology, applied in the direction of static indicators, instruments, etc., can solve the problems of accelerating the output fall time, shortening the line time, increasing the load, etc., to save area, reduce the fall time, and reduce the size of the drive tube Effect

Active Publication Date: 2019-06-07
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] This application provides a high-speed gate drive unit and a gate drive circuit composed of the high-speed gate drive unit, which solves the problems of sharply increased load and shortened row time faced by high-definition large-size display panels, and enhances the performance of the drive tube on the grid. The discharge capacity of the load on the pole scan line can speed up the output fall time and meet the requirements of the high-definition large-size display for the fall time of the line scan signal

Method used

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  • A high-speed grid driving unit and a circuit
  • A high-speed grid driving unit and a circuit
  • A high-speed grid driving unit and a circuit

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Embodiment 1

[0059] Please refer to Figure 4, is a schematic structural diagram of a high-speed gate driving unit disclosed in Embodiment 1 of the present invention. As shown in the figure, the high-speed gate driving unit of the embodiment of the present invention includes an input and reset unit 10 , an inverter unit 20 , a down-coupling unit 30 , an output driving unit 40 and a low-level maintaining unit 50 . The input and reset unit 10 is configured to receive a first clock signal and a first input signal, and charge an internal node Q1 to a high potential through the first input signal when the first clock signal is at a high level, and then When the first input signal is at a low level, the internal node Q1 is reset to a low level by the first clock signal. The inverter unit 20 is used to generate the control signal of the low level maintaining unit 50 and the coupling signal of the down coupling unit 30, and receive the second clock signal during the falling phase of the scanning ...

Embodiment 2

[0070] Please refer to Figure 6 , on the basis of Embodiment 1, the high-speed gate drive unit of an embodiment further includes an up-coupling unit 60 and a cascade generation unit 70; the up-coupling unit 60 is used to couple the potential of a cascade signal to the internal node Q1 to increase the potential of the internal node Q1. The cascade generation unit 70 is configured to receive the third clock signal and output the cascade signal when the internal node Q1 is at a high potential, and accelerate the third clock signal to be high through the internal node Q1 whose potential is raised When the level is low, the pull-up of the cascaded signal is charged and / or the output amplitude of the cascaded signal is increased.

[0071] In the embodiment of the present invention, the cascade generation unit 70 receives the third clock signal and outputs the cascade signal when the internal node Q1 is at a high potential, and the cascade signal is outputted through the rising cou...

Embodiment 3

[0077] Please refer to Figure 8 ,exist Figure 7 Based on the above, the high-speed gate drive unit in one embodiment further includes an isolation unit 80 for isolating the influence of the internal node Q1 on the potential of the internal node Q2 when the potential of the internal node Q1 is lower than the potential of the internal node Q2 and / or, when the potential of the internal node Q1 is higher than the potential of the internal node Q2, charge the internal node Q2 through the internal node Q1 to increase the potential of the internal node Q2.

[0078] In the embodiment of the present invention, the isolation unit 80 is used to isolate the internal node Q1 and the internal node Q2, suppress the reverse current from the internal node Q2 to the internal node Q1, or suppress the reverse current from the internal node Q1 to the internal node Q2 reverse current, so that the potentials between the internal node Q1 and the internal node Q2 will not interfere with each other....

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Abstract

The invention discloses a high-speed grid driving unit and a circuit, and the circuit comprises an input and reset unit which transmits a high-level signal of a first input signal to an internal nodeQ1 when a first clock signal is at a high level, so that the Q1 is charged to a high level; an inverter unit which is used for receiving the high-level second clock signal, charging the internal nodeQB to a high level through a high-voltage input signal VH, and coupling the high level of the QB to the internal node Q2 through the descending coupling unit to improve the potential of the Q2; an Output driving unit, wherein when Q1 is at a high potential, the output drive unit is enabled, the pull-down discharge of the scanning signal is accelerated when the third clock signal is at a low levelthrough the Q2 with the increased potential. By increasing the overdrive voltage and enhancing the discharge capacity, when the QB is at a high potential, the low-level maintaining unit pulls down a scanning signal through a low-voltage input signal VSS and maintains the scanning signal at a low level, the driving tube and the pull-down tube are conducted at the same time, the discharge current loaded on the scanning line is increased, and the reduction speed of the scanning signal is increased.

Description

technical field [0001] The present application relates to the field of display technology, in particular to a high-speed gate drive unit and circuit. Background technique [0002] In recent years, active matrix flat panel display technology has developed rapidly, and large-size, high-resolution display is an important development direction. Integrated gate driver on array (GOA) is an important technology in the development of large-scale and high-resolution displays. The integrated gate drive circuit is a technology that integrates the row scanning circuit on the TFT substrate. For high-definition large-size display panels, the gate scanning lines increase sharply, requiring more gate driver chips, which not only increases the cost, but also reduces the integration yield due to too many gate scanning lines in the bonding process. Compared with the traditional gate drive chip technology, the integrated gate drive circuit saves the bonding area between the chip and the panel...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/20
Inventor 张盛东雷腾腾廖聪维黄杰
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL
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