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Method for optimizing memory access distance on many-core processor

A technology of many-core processors and memory distance, which is applied in the field of computer compilation, can solve the problems of poor memory access efficiency and achieve the effects of enhancing operating efficiency, improving locality and cache utilization

Inactive Publication Date: 2019-06-07
BEIJING INSTITUTE OF TECHNOLOGYGY +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] At present, there are defects in the optimization of memory access efficiency on many-core processors, resulting in excessive independence between each core, making the overall memory access efficiency poor

Method used

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Embodiment Construction

[0013] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0014] In an embodiment of the present invention, a method for optimizing a memory access distance of a many-core processor includes generating an inter-kernel pipeline scheduling table, optimizing the memory access distance of the many-core processor according to the inter-kernel pipeline scheduling table, and optimizing communication;

[0015] The steps of generating the pipeline scheduling table between kernels are as follows: firstly, divide the synchronous data flow graph into process-level tasks, and determine the corresponding...

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Abstract

The invention discloses a method for optimizing a memory access distance on a many-core processor. The method comprises the following steps: generating an inter-kernel pipeline scheduling table, and performing memory access distance optimization and communication optimization on a many-core processor according to the inter-kernel pipeline scheduling table, and the step of generating the inter-kernel pipeline scheduling table specifically comprises the following steps: firstly, performing process-level task division on a synchronous data flow diagram, and determining a corresponding cluster node to which each calculation task is allocated; secondly, conducting thread-level task division on tasks in the synchronous data flow diagram in the cluster nodes, and determining processing cores, distributed to the computing tasks, in the corresponding cluster nodes. According to the method, use of caches in a many-core processor is optimized, the locality of data access and the cache utilizationrate are improved, and the running efficiency of a program is improved.

Description

technical field [0001] The invention relates to the field of computer compilation, in particular to a method for optimizing memory access distances on many-core processors. Background technique [0002] Data operation and processing capabilities have become the core competitiveness of an enterprise and even a country. In China, major strategic layouts such as cloud computing, Internet of Things, triple play integration, and broadband speed-up have been accelerated at an unprecedented speed, further expanding and deepening the scope and depth of the data explosion. impact, which intensifies the further demand for high performance and high stability of the network. As the core of the data communication network, router equipment has become a key factor restricting the performance of data services; in particular, cloud computing applications in data concentration are becoming more and more popular, and the demand for high-end core routers is also increasing day by day. Many-cor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50
Inventor 张瑞田密
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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