A low complexity and fast SIFT feature extraction method based on FPGA

Abstract

The invention relates to the field of computer vision, in order to optimize the feature descriptor extraction part of the SIFT algorithm, improve the hardware execution speed of the part, maintain thestability of the feature descriptor, and reduce the consumption of FPGA hardware resources. To this end, The technical scheme adopted by the invention is as follows: A low-complexity and fast SIFT feature extraction method based on FPGA utilizes an upsampling module to collect image data to an initial two-dimensional Gaussian filter module G0 to generate a reference Gaussian image, and then utilizes four parallel two-dimensional Gaussian filters G1 to G4 to generate four-layer Gaussian images to form a Gaussian pyramid. Gaussian difference images D1 to D3 obtained by subtracting two adjacentGaussian images constitute a Gaussian difference pyramid. The invention is mainly applied to image feature extraction occasions.

Description

technical field [0001] The invention relates to the field of computer vision, relates to a real-time target recognition system based on FPGA (Field Programmable Gate Array), in particular to a fast SIFT feature extraction technology based on FPGA. Background technique [0002] In the field of computer vision, the scale invariant feature transform (SIFT) algorithm is widely used. The main idea of ​​the SIFT algorithm is to first detect stable feature points in the image, and then extract local feature descriptors in the neighborhood of feature points. The main steps are as follows. [0003] (1) Perform preprocessing on the input image including upsampling and initial Gaussian filtering, and then construct a Gaussian pyramid and a Gaussian difference pyramid. [0004] (2) Detect feature points in the Gaussian difference pyramid. [0005] (3) Calculate the main direction of the feature points. [0006] (4) Rotate the feature point neighborhood according to the main direction...

AI Technical Summary

Problems solved by technology

However, these two acceleration methods have the disadvantage of high power consumption and cannot be applied in embedded systems.

[0008] Because the Field Programmable Gate Array (FPGA) has the characteristics of high speed and low power consumption, many researchers use FPGA to accelerate the SIFT algorithm, so that the number of clock cycles required to extract feature points is getting closer and closer to the number of image pixels, feature description The symbol extraction part gradually becomes the bottleneck that limits the hardware execution time

Images