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Wafer level packaging structure of chip, and preparation method of wafer level packaging structure

A wafer-level packaging and chip technology, applied in electrical components, circuits, semiconductor devices, etc., to overcome chip short-circuits, improve welding strength and sealing effect

Inactive Publication Date: 2019-02-15
XIAN TRANSETERNAL ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a chip wafer-level packaging structure and its preparation method to solve the problem of welding and packaging of small and low-cost infrared detectors in the prior art

Method used

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  • Wafer level packaging structure of chip, and preparation method of wafer level packaging structure
  • Wafer level packaging structure of chip, and preparation method of wafer level packaging structure
  • Wafer level packaging structure of chip, and preparation method of wafer level packaging structure

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Embodiment 1

[0036] This embodiment provides a chip wafer-level packaging structure, including a chip 1, and also includes a vacuum cavity structure, and the vacuum cavity structure encapsulates the chip 1 inside; wherein, the vacuum cavity structure includes a silicon chip supporting shell 2, a silicon chip The upper surface of the support shell 2 is provided with a first anti-reflection film 5, and the inner surface of the silicon chip support shell 2 is provided with a second anti-reflection film 4 at a position opposite to the first anti-reflection film 5, and the second anti-reflection film 4 A getter film 3 is provided next to the chip 1; a first solder ring 7 is provided on the periphery of the chip 1, a second solder ring 8 and a third solder ring are provided on the bottom of the silicon chip supporting shell 2, and the first solder ring 7 and the second The solder ring 8 and the third solder ring 9 are sealed by bonding in a vacuum environment.

[0037] In this embodiment, the en...

Embodiment 2

[0045] A method for preparing a wafer-level packaging structure of a chip, comprising the following steps:

[0046]Step 1, one side of the silicon wafer supporting shell 2 is first made a scribe line by photolithography and etching; the other side of the silicon wafer supporting shell 2 is made a 100 μm deep cavity by photolithography and etching;

[0047] Step 2, vapor-depositing the second anti-reflection film 4 and the getter film 3 on the bottom of the deep cavity;

[0048] Step 3, evaporate the second solder ring 8, the second anti-overflow bar 602 and the third solder ring 9 on the step of the deep cavity;

[0049] Step 4, making a scribe line on the backside of the silicon wafer of the chip 1 by photolithography and etching; evaporating the first solder ring 7 and the first anti-overflow strip 601 on the front side of the silicon wafer of the chip 1;

[0050] Step 5, vacuumize the silicon wafer supporting the shell 2 and the silicon wafer of the chip 1 in the bonding m...

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Abstract

The invention provides a wafer level packaging structure of a chip. The wafer level packaging structure comprises a chip, and further comprises a vacuum cavity structure, wherein the chip is packagedinside the vacuum cavity structure; the vacuum cavity structure comprises a silicon wafer supporting shell; a first antireflection film is arranged on the upper surface of the silicon wafer supportingshell; a second antireflection film is arranged at the position, opposite to the first antireflection film, of the inner surface of the silicon wafer supporting shell; a getter film is arranged beside the second antireflection film; a first solder ring is arranged on the periphery of the chip; a second solder ring and a third solder ring are arranged at the bottom of the silicon wafer supportingshell; and the first solder ring and the third solder ring are bonded and sealed in a vacuum environment to form the vacuum cavity structure.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a chip wafer-level packaging structure and a preparation method thereof. Background technique [0002] Infrared detectors are the core components of thermal imaging systems and the key to detecting, identifying and analyzing infrared information of objects. They are widely used in various industries such as military, industry, transportation, security monitoring, meteorology, and medicine. Traditional infrared detectors are mainly packaged at the chip level, using metal or ceramic shells. The overall quality is heavy, the volume is large, and the cost is high. The packaging cost accounts for 90% of the entire detector cost, which is not conducive to the market application and promotion of the product. [0003] Wafer-level packaging is to add a capped silicon chip directly on the wafer after the entire wafer is produced, and uniformly package a single chip throu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/0203
CPCH01L31/0203
Inventor 杨健雄
Owner XIAN TRANSETERNAL ELECTRONICS
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