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Out-of-order block-based processors and instruction schedulers

A processor and scheduler technology, applied in instruction analysis, running instruction conversion, concurrent instruction execution, etc., can solve problems such as continuous improvement in area or performance

Active Publication Date: 2018-12-21
MICROSOFT TECH LICENSING LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Out-of-order superscalar implementations have not shown consistent improvements in area or performance

Method used

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  • Out-of-order block-based processors and instruction schedulers
  • Out-of-order block-based processors and instruction schedulers
  • Out-of-order block-based processors and instruction schedulers

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Embodiment Construction

[0019] I. overall consideration

[0020] The present disclosure is set forth in the context of representative embodiments which are not intended to be limiting in any way.

[0021] As used in this application, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. Also, the term "comprising" means "comprising". Furthermore, the term "coupled" encompasses mechanical, electrical, magnetic, optical, and other practical means of coupling or linking items together and does not exclude the presence of intervening elements between coupled items. Additionally, as used herein, the term "and / or" means any one or a combination of multiples of the phrase.

[0022] The systems, methods and devices described herein should not be construed as limiting in any way. Rather, the present disclosure is directed to all novel and non-obvious features and aspects of the various disclosed embodiments both alone and in various combinations an...

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PUM

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Abstract

Apparatus and methods are disclosed for implementing block-based processors including field programmable gate-array implementations. In one example of the disclosed technology, a block-based processorincludes an instruction decoder configured to generate decoded ready dependencies for a transactional block of instructions, where each of the instructions is associated with a different instructionidentifier encoded in the transactional block. The processor further includes an instruction scheduler configured to issue an instruction from the set of transactional block of instructions out of order. The instruction is issued based on determining that decoded ready state dependencies for an instruction are satisfied. The determining includes accessing storage with the decoded ready dependencies indexed with a respective instruction identifier that is encoded in the transactional block of instructions.

Description

Background technique [0001] Due to the continued transistor scaling predicted by Moore's Law, microprocessors have benefited from continued increases in transistor count, integrated circuit cost, manufacturing capital, clock frequency, and energy efficiency, while the associated processor instruction set The architecture (ISA) has changed very little. However, the benefits realized from the lithographic scaling that has driven the semiconductor industry for the past 40 years are slowing or even reversing. The Reduced Instruction Set Computing (RISC) architecture has been the dominant paradigm in processor design for many years. Out-of-order superscalar implementations have not shown consistent improvements in area or performance. Therefore, there is ample opportunity for improvements in processor ISAs to scale performance improvements. Contents of the invention [0002] Methods, apparatus, and computer-readable storage devices for configuring, manipulating, and compiling ...

Claims

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Application Information

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IPC IPC(8): G06F9/38
CPCG06F9/3017G06F9/30181G06F9/30185G06F9/3818G06F9/3834G06F9/3873G06F9/3889G06F9/3897G06F9/3836G06F9/3838Y02D10/00G06F9/3858G06F15/7867G06F9/3856G06F9/3016G06F9/3885G06F9/3005
Inventor A·L·史密斯J·S·格雷
Owner MICROSOFT TECH LICENSING LLC
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