Anti-irradiation high-order high-speed parameter-reconstructable FIR filter design method and system

Abstract

The invention discloses an anti-irradiation high-order high-speed parameter-reconstructable FIR filter design method and system. The anti-irradiation high-order high-speed parameter-reconstructable FIR filter design method includes the following steps: 1) according to a task demand, determining an order N of an FIR filter; 2) according to an FPGA model, determining the number L of multiply add accumulators (MAC) contained in one column of MACs; 3) if N <=L, completing design of the filter by using a low-order FIR filter design method based on a hard core of MAC; and 4) if N>L, completing design of the filter by using a high-order FIR filter design method based on a hard core of MAC. The anti-irradiation high-order high-speed parameter-reconstructable FIR filter design method and system hasthe advantages of high operation speed, few occupied resources and high order, and is suitable for design of a satellite payload FIR filter.

Description

technical field [0001] The invention belongs to the technical field of satellite navigation, and in particular relates to a design method and system for an anti-irradiation high-speed high-speed parameter reconfigurable FIR filter. Background technique [0002] Because of its simple structure and linear phase characteristics, FIR filters are widely used in the design of various navigation and communication satellite payloads. At present, the realization of the FIR filter in the FPGA is mostly realized by combining the hard core of the multiplier in the FPGA and SLICE. This method uses the hard core of the multiplier to realize the multiplication function, and the SLICE realizes the addition function. This method is intuitive and simple to implement, but it has the disadvantages of low running speed, large resource consumption, low order, susceptible to the influence of space radiation and FIR filter parameters cannot be reconfigured. In detail, the FIR filter used on the sa...

AI Technical Summary

Problems solved by technology

[0003] (1) Susceptible to Single Event Upset (SEU)

[0004] SRAM type FPGAs are susceptible to SEU and have low reliability

[0005] (2) Large resource consumption

[0006] A large number of multi-bit adders are used in the FIR filter, which consumes a lot of resources

[0007] (3) Timing is very tight

If the multi-bit adder is built with multi-stage SLICE, it will inevitably lead to a huge operation delay

The combinational logic delay between the two flip-flops is too large, which will cause the sequential logic to fail to meet the clock rate operation requirements

[0009] (4) low order

[0010] Due to the difficulty of taking into account the high operation rate and high order number when using SLICE, the use conditions and environment on the star are limited

[0011] (5) FIR filter parameters cannot be reconstructed

[0012] The FIR filter IP core provided by Xilinx cannot flexibly reconstruct the parameters of the FIR filter, resulting in a design that is not flexible enough to meet the needs of the design

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