A method for executing logarithmic load instruction

Abstract

The invention discloses a method for executing a logarithmic load instruction. The steps include taking out an LDP instruction and splitting it into two micro-operations. Each micro-operation has a purpose register. The micro-operation is used as a unit to perform decoding and register renaming. And dispatch, when dispatching, assign one item to each of the two micro-operations in the reorder buffer, and merge the two micro-operations in the emission queue; if both data loading pipelines are available, the merged LDP will be emitted to the memory access unit , and execute in the first data loading pipeline; after the execution, the lower half of the obtained data will be written back to the first destination register through the result bus of the first data loading pipeline, and the upper half will be written back to the first destination register through the second data loading pipeline. The result bus is written back to the second destination register; finally, two micro-ops are submitted to release resources. The invention can reduce the number of destination register channels, reduce design complexity and save area cost without increasing the number of data access times.

Description

technical field [0001] The invention relates to the field of microprocessor design, in particular to an execution method of a logarithmic load instruction in the design of an out-of-order superscalar microprocessor. Background technique [0002] For an instruction set architecture, most instructions have no more than one destination register. However, some instruction set architectures provide a pair of load instructions. We use the mnemonic LDP Rd1, Rd2, Xn, #offset to represent the instruction, where Rd1 and Rd2 are the destination registers, Xn is the memory base address, and #offset is the address offset. Shift, hereinafter also use LDP as the abbreviation of logarithmic load instruction. The logarithmic load instruction has two destination registers, namely Rd1 and Rd2, which means to read data whose width is twice the width of a destination register from address [Xn+offset], and store the lower half of the data into Rd1 , the high half is stored in Rd2. Because LDP ...

AI Technical Summary

Problems solved by technology

In order to support a pair of load instructions, the maximum number of rename registers released per beat will be doubled, thereby increasing the design complexity of the logic

[0005] In the known out-of-order superscalar microprocessor design, in order to support a pair of load instructions, one register channel is added from the decoding stage until the instruction is submitted, thereby increasing the design complexity and implementation cost

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