Near data stream computing acceleration array based on RISC-V

Abstract

The invention provides a near data stream computing acceleration array based on RISC-V. The near data stream computing acceleration array comprises an RSIC-V core and an acceleration array which is arranged around the RSIC-V core and is composed of a plurality of coprocessors. Each coprocessor comprises an NOC routing control node, an RAM block and a multiply-add particle. Wherein the RAM block isused for realizing caching of to-be-calculated data, the multiply-add particle is used for realizing multiply-accumulate calculation, and the NOC routing control node realizes interconnection with other adjacent coprocessors on one hand, and is also connected with the data RAM block and the multiply-add particle on the other hand. According to the method, to-be-calculated data is dispersedly stored in a plurality of ram blocks, and multiply-add calculation operators are placed as close as possible to rams. Adjacent coprocessors are interconnected by adopting an on-chip network structure, andthe relationship between a producer and a consumer is realized in a calculation process. Therefore, one calculation process can be converted into a process that a data stream flows between the coprocessor acceleration arrays for calculation after being split and mapped.

Description

technical field [0001] The invention relates to a RISC-V-based near-data streaming computing acceleration array. Background technique [0002] The von Neumann architecture is a classic architecture of computers, and it is also the mainstream architecture of current computers and processor chips. In the von Neumann architecture, the computing / processing unit and storage are two completely separate units: the computing / processing unit reads data from the storage device, completes the computing / processing in the computing / processing unit, and stores it back in the storage unit . This is a typical computing-centric computing structure. In order to realize the calculation of data, it is necessary to trigger a large number of data movement actions. Although the main frequency and number of computing cores are constantly increasing, the access rate of peripheral memory has not been increased synchronously. The throughput of the data bus can easily become a system bottleneck. The...

AI Technical Summary

Problems solved by technology

In the process of architecture design, the amount of data required for computing represented by artificial neural networks is huge, and the problem of memory walls is serious. Therefore, the main contradiction to be solved first is how to shorten the "distance" between data storage and computing units as much as possible. And minimize the access to the memory during the calculation process, while maintaining a certain degree of flexibility and elasticity to meet the variability and elastic deployment requirements of future neural network algorithms and different signal processing computing scenarios

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