Duty cycle calibration circuit

Abstract

The embodiments of the present invention disclose a duty cycle calibration circuit. The duty cycle calibration circuit includes a delay line, a falling edge detection module, and a phase interpolationmodule; the delay line is connected in series with a plurality of sub-delay lines; each sub-delay line includes one or more series delay units of which the delay time is equal, the delay time of thedelay units in the previous sub-delay line being shorter than the delay time of the delay units in the next sub-delay line; and the falling edge detection module is used to obtain a plurality of delaysignals of signals to be calibrated from the delay lines according to the frequency of the signals to be calibrated, and detect the falling edge of the signals to be calibrated according to the signals to be calibrated and each of the delay signals, so as to obtain falling edge state detection signals; and the phase interpolation module is used to obtain calibrated signals according to the signals to be calibrated and the falling edge detection signals. The power consumption and area of the circuit can be reduced with the duty ratio calibration precision of signals of different frequencies satisfied.

Description

technical field [0001] The present application relates to the technical field of signal processing, and in particular to a duty cycle calibration circuit. Background technique [0002] In a high-speed digital system, the duty cycle jitter of the high-speed clock signal will lead to unstable operation of the system. A duty cycle correction circuit (duty cycle correction, DCC) needs to be added to solve the problem of the duty cycle jitter of the high-speed clock. The duty cycle is corrected to 50% to ensure the normal operation of the system. [0003] A currently commonly used duty ratio calibration circuit is a duty ratio calibration circuit with a digital open-loop structure, including a delay line, a logic control module and a phase interpolation module (phase interpolation, PI). The delay line is composed of a plurality of delay cells connected in series, and is used to delay the phase of the input signal by a unit time. The logic control module uses the signal to be ca...

AI Technical Summary

Problems solved by technology

[0004] Since the calibration accuracy of the duty cycle is related to the delay time of each delay unit, for high-frequency signals, the high precision of the calibration requires a short delay time of the delay unit; for low-frequency signals, if the delay The delay time of the unit is short, and a large number of delay units are required to achieve high precision of duty cycle calibration, and the area occupied by the duty cycle calibration circuit is large

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