CMOS digital integration circuit board manufacturing process

Abstract

The present invention discloses a CMOS digital integration circuit board manufacturing process. The manufacturing process comprises the following steps of: S1, selection of a substrate; S2, manufacturing of an n well; S3, oxidation of court areas; S4, manufacturing of a polysilicon gate; S5, formation of a source region and a drain region; S6, formation of a metal interaction wire; and S7, coverage of a layer of phosphorosilicate glass passive film on a silicon wafer after formation of the metal interaction wire to perform once photoetching to expose a leading-out terminal and pressure pointsof a silicon wafer of the integration circuit and connect the pressure points of the silicon wafer and corresponding pins of a tube.

Description

technical field [0001] The invention relates to the technical field of integrated circuit boards, in particular to a manufacturing process of CMOS digital integrated circuit boards. Background technique [0002] CMOS digital integrated circuit board is a complementary circuit composed of PMOS and NMOS. PMOS needs an n-type substrate, and NMOS needs a p-type substrate. In a CMOS circuit, PMOS and NMOS should be fabricated on one substrate. The CMOS circuit solves this problem by making a well. According to the structure, CMOS circuits can be divided into three types: n-well CMOS, p-well CMOS and double-well CMOS. [0003] The current manufacturing process of CMOS digital integrated circuit boards cannot activate impurities and make impurities reach deep distribution at the same time; the isolation effect between devices is poor; the gate connection between NMOS and PMOS is inconvenient; the channel length cannot be accurately controlled. Parasitic capacitance and the inabil...

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Problems solved by technology

[0003] The current manufacturing process of CMOS digital integrated circuit boards cannot activate impurities and make impurities reach deep distribution at the same time; the isolation effect between devices is poor; the gate connection between NMOS and PMOS is inconvenient; the channel length cannot be accurately controlled. Parasitic capacitance and the inability to completely guarantee the mutual isolation between different conductive layers

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