Hash hybrid acceleration system and method for applying it to hash join

Abstract

A hash mixing acceleration system and a hash connection method using the same. The system includes: a hash partition accelerator, which is configured to be integrated on the memory, and is used to accelerate the processing of the hash join partition stage. The hash partition accelerator includes: a hash unit used to read multiple block relational tables from memory Tuples, and then process the keys of multiple tuples in parallel to generate multiple hash indexes; the histogram unit is used to update multiple copies of the histogram data stored in the histogram unit in parallel according to multiple hash indexes , and the updated copies are integrated into a form of data consistency; the shuffling unit is used to determine the location of each tuple stored in the target address array based on multiple hash indexes, and copy the tuples in the relational table to An array of targets; the host processor that handles the construction and probing phases of the hash join. Compared with existing processors, the disclosed hybrid acceleration system can greatly improve the energy efficiency of hash join processing.

Description

technical field [0001] The disclosure relates to the field of computer systems, and further relates to a hash mixing acceleration system and a hash connection method using the hash mixing acceleration system. Background technique [0002] The first factor to consider when designing a modern computer system is power consumption. To improve energy efficiency, hardware accelerators such as Field Programmable Gate Arrays (FPGAs), Graphics Processing Units (GPUs) and custom accelerators have been widely used in industry. With the advent of processing technology close to the data, integrating hardware accelerators into the dynamic random access memory (DRAM) stack to reduce the cost of data movement has become a new system design idea. The basic idea is to use 3D stacking technology to vertically integrate some logic dies including accelerators and multiple DRAM dies into one chip. However, the number and types of accelerators that can be integrated into DRAM are limited due to ...

AI Technical Summary

Problems solved by technology

However, the number and types of accelerators that can be integrated into DRAM are limited due to the limitations of 3D stacked DRAM in terms of area, power consumption, heat dissipation, and manufacturing.

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