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Method and system for locating winding congestion in chip design

A chip design and winding technology, applied in CAD circuit design, calculation, special data processing applications, etc., can solve problems such as affecting chip function, delaying chip tape-out, reducing chip competitiveness, etc., to improve design efficiency and reduce code. Effects of modification risk and extensive verification work to ensure physical achievability

Inactive Publication Date: 2018-06-15
SUZHOU CENTEC COMM CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is easy to affect the function of the chip by modifying the code, and it will delay the tape-out of the chip, delay the time to market, and reduce the competitiveness of the chip
[0003] In addition, the common way to locate the routing congestion is to define a detection area, and then analyze the routing congestion in the area. Usually, the detection area includes multiple sub-modules. The efficiency of locating the routing congestion in this way is low.

Method used

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  • Method and system for locating winding congestion in chip design
  • Method and system for locating winding congestion in chip design
  • Method and system for locating winding congestion in chip design

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Embodiment Construction

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention.

[0042] The method and system for locating winding congestion in chip design disclosed by the present invention can quickly discover and locate the underlying sub-module in the chip where winding congestion occurs, and is especially suitable for the RTL design stage of the chip.

[0043] Such as figure 1 As shown, a method for locating winding congestion in a chip design according to the present invention includes the following steps:

[0044] S1, obtain the gate-level netlist, and obtain the total number of windings and the total area of ​​each underlying sub-module in the gate-level netlist;

[0045] Specifically, the gate-level netlist can be obtained through the logic synthesis tool Design Complier, which converts the circuit described in the RTL (Register Transfer Level, register...

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Abstract

The invention discloses a method and a system for locating winding congestion in chip design. The method comprises the steps of obtaining a gate-level netlist, and obtaining a total winding number anda total area of each bottom sub-module in the gate-level netlist; and according to the total winding number and the total area of each bottom sub-module, obtaining winding congestion of each bottom sub-module, and according to the winding congestion, locating the bottom sub-module with the winding congestion. The bottom sub-module with the winding congestion in a chip can be quickly discovered and located in chip design and comprehensive stages, so that the physical realizability of the chip is ensured.

Description

technical field [0001] The invention relates to the field of chip design, in particular to a method and system for locating winding congestion in chip design. Background technique [0002] The chip design process in integrated circuits includes the front-end design stage and the back-end physical realization stage. The front-end design stage includes logic design and synthesis, etc., and the back-end physical realization stage includes wiring. Routing congestion in chip design is generally not exposed and discovered until the back-end physical implementation stage. Routing congestion is a situation where the wires cannot be bypassed due to too many wires in a certain area during the physical implementation of the chip. If winding congestion is found in the physical implementation stage, the code in the front-end design stage needs to be modified to solve the problem of winding congestion. It is easy to affect the function of the chip by modifying the code, and it will dela...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/30
Inventor 段光生许俊唐飞
Owner SUZHOU CENTEC COMM CO LTD
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