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Manufacturing method for semiconductor structure

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, electric solid state devices, electrical components, etc., can solve problems such as damage to the ONO structure in the SONOS storage area

Inactive Publication Date: 2018-06-12
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is that at present, in the semiconductor process of integrating 5V devices and SONOS memory, when removing the gate hard mask layer of the 5V device region, it is necessary to add a photomask process, and the photomask is not currently used. The method of removing the gate hard mask layer (such as 55nm HV process) will cause damage to the ONO structure of the SONOS storage area

Method used

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  • Manufacturing method for semiconductor structure
  • Manufacturing method for semiconductor structure
  • Manufacturing method for semiconductor structure

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Embodiment Construction

[0020] In order to make the object, technical solution and advantages of the present invention clearer, the method for fabricating the semiconductor structure of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be noted that all the drawings are in very simplified form and use inaccurate scales, which are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0021] The terms "first", "second", etc. in the description and claims are used to distinguish between similar elements and not necessarily to describe a specific order or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances, for example, to enable the embodiments of the invention described herein to be operated in other sequences than described or illustrated herein. Similarly, if a method described herein includes ...

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Abstract

The invention relates to a manufacturing method for a semiconductor structure, and the method comprises the steps: forming an ONO structure in an SONOS storage region, wherein the ONO structure comprises a surface covering layer which covers the top and side surfaces; forming a first gate structure in a 5V device region, wherein the first gate structure comprises a first gate hard mask layer; forming a second gate structure in the SONOS storage region, wherein the second gate structure comprises a second gate hard mask layer; carrying out the LDD ion implantation in the 5V device region 110. Because of the protection of the surface covering layer, the method can reduce or avoid the impact on a nitridation layer in the ONO structure from the etching and removing process of the first gate hard mask layer after the LDD ion implantation, and further forms the surface covering layer through the ISSG technology, and is lower in cost.

Description

technical field [0001] The present invention relates to the field of semiconductor fabrication, and more specifically, the present invention relates to a fabrication method of a semiconductor structure. Background technique [0002] 5V voltage is an input and output voltage widely used at present. In practice, 5V devices are usually used to design input and output circuits, so there is a wide demand for 5V devices. SONOS (silicon-oxide-nitride-oxide-silicon, silicon-oxide-nitride-oxide-silicon) memory is a common memory, and its basic storage unit usually includes a SONOS tube and a selection tube, a In the manufacturing method of the semiconductor structure, the 5V device and the SONOS memory are integrated on the same silicon wafer. [0003] In the semiconductor process integrating 5V devices and SONOS memory, due to the high injection energy required for 5V devices, silicon nitride is usually used as the gate hard mask layer in the fabrication process of 5V devices to pr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/1157H10B43/35
CPCH10B43/35
Inventor 黄冠群戴树刚
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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