Distinct system registers for logical processors

Abstract

Distinct system registers for logical processors are disclosed. In one example of the disclosed technology, a processor includes a plurality of block-based physical processor cores for executing a program comprising a plurality of instruction blocks. The processor also includes a thread scheduler configured to schedule a thread of the program for execution, the thread using the one or more instruction blocks. The processor further includes at least one system register. The at least one system register stores data indicating a number and placement of the plurality of physical processor cores toform a logical processor. The logical processor executes the scheduled thread. The logical processor is configured to execute the thread in a continuous instruction window.

Description

Background technique [0001] Due to the continued transistor scaling predicted by Moore's Law, microprocessors have benefited from continued increases in transistor count, integrated circuit cost, manufacturing capital, clock frequency, and energy efficiency, while the associated processor instruction set architecture (ISA) has Little changes. However, the benefits realized from the lithographic expansion that has driven the semiconductor industry for the past 40 years are slowing or even reversing. The Reduced Instruction Set Computing (RISC) architecture has been the dominant paradigm in processor design for many years. Out-of-order superscalar implementations have not shown consistent improvements in area or performance. Thus, there is ample opportunity for processor ISA improvements to scale performance improvements. Contents of the invention [0002] Methods, apparatus, and computer-readable storage devices for combining one or more resources of a processor core into ...

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Problems solved by technology

Therefore, there is ample opportunity for processor ISA improvements to scale performance improvements

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