Method for rapidly positioning short circuit of three-dimensional memory array zone

Abstract

The invention provides a method for rapidly positioning short circuit of a three-dimensional memory array zone, which includes steps of processing a to-be-tested sample to a tungsten plug layer; marking a failure zone block of the processed to-be-tested sample by a focusing ion beam machine table; applying a certain voltage to the tungsten plug of a step zone through a nano-point needle table, andfinding out a failure path between an array zone word line layer and the word line layer or between the word line layer and a source electrode; applying the focusing ion beam machine table to draw out a line at the tungsten plug of the step zone corresponding to the failed word line layer; then depositing a metal cushion body at the tail end of the line; applying a certain voltage to the metal cushion body through a micro-light microscope and thereby highlighting the hot spot signal at the failure place; marking a laser mark at the failure point; performing section cutting on the laser marking place by the focusing ion beam machine table while observing the failure point, and preparing a transmission electron microscopy test block; representing the test block by the transmission electronmicroscopy. The method can rapidly position and represent the short circuit point of the word line layer.

Description

technical field [0001] The invention relates to a failure analysis method, in particular to a method for quickly locating a short circuit in a three-dimensional memory array area. Background technique [0002] In the process of semiconductor research and development and production, failure analysis is an indispensable means to improve the process and increase the yield. In the failure analysis process, the most basic and important step is the location of the failure point. The accuracy of location directly affects the subsequent analysis. Therefore, how to obtain an accurate failure location is particularly critical. However, in the current three-dimensional memory products, the structure of the memory array area is a word line layer stacking mode. As the number of stacked layers increases (≥32 layers), the range of the array area becomes larger (≥3mm*6mm), and the array Zone failure will be the dominant failure mode. For failures of the type of short circuit between word ...

AI Technical Summary

Problems solved by technology

[0003] Existing technologies cannot accurately locate and characterize short-circuit failure points between word line layers and between word line and source in the three-dimensional memory array area

The instability of the three-dimensional memory process leads to short circuits between the word line layer and the word line layer in the array area, and between the word line layer and the source, thus affecting the performance of the product

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