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memory system and processor system

A memory system and memory technology, applied in memory systems, electrical digital data processing, input/output process of data processing, etc. The effect of spatial locality optimization

Active Publication Date: 2021-05-28
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Temporal locality and spatial locality are in a trade-off relationship. It is possible that if temporal locality is emphasized, spatial locality cannot be guaranteed, and if spatial locality is emphasized, temporal locality cannot be guaranteed.

Method used

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  • memory system and processor system

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Experimental program
Comparison scheme
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no. 1 Embodiment approach

[0031] figure 1 It is a block diagram showing a schematic configuration of the processor system 2 including the memory system 1 according to the first embodiment. figure 1 The processor system 2 includes a processor 3 and a main memory 4 . The main memory 4 constitutes at least a part of the memory system 1 .

[0032] Inside the processor 3, a first memory controller 5 is provided. In addition, inside the processor 3, a plurality of processor cores, cache memory, etc. are provided, but in figure 1 omitted. The first memory controller 5 controls the second memory controller 6 in the main memory 4 . More specifically, the first memory controller 5 controls the second memory controller 6 in accordance with an access request to the main memory 4 .

[0033] The main memory 4 includes a first memory 7 and a memory module 8 in addition to the above-mentioned second memory controller 6 . The first memory 7 is, for example, a nonvolatile memory such as MRAM (Magnetoresistive Rand...

no. 2 Embodiment approach

[0082] Figure 11 It is a block diagram showing a schematic configuration of a processor system 2 including a memory system 1 according to the second embodiment. Figure 11 The processor system 2 includes a processor core 31 and a memory system 1 . The memory system 1 has a primary cache memory (hereinafter L1 cache) 32, a secondary cache memory (hereinafter L2 cache) 33, a tertiary cache memory (hereinafter L3 cache) 34, and a fourth cache memory (hereinafter L4 cache) 35 and memory access controller 24. right Figure 11 Although the main memory 4 is connected to the memory system 1, the main memory 4 may be provided inside the memory system 1.

[0083] The L1 cache 32 is connected to the processor core 31 and the L2 cache 33 . The L2 cache 33 is connected to the L1 cache 32 and the L3 cache 34 . The L3 cache 34 is connected to the L2 cache 33 and the L4 cache 35 . The memory access controller 24 is connected to the L4 cache 35 .

[0084] The data stored in the main me...

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Abstract

Embodiments of the invention relate to memory systems as well as processor systems. Provided are a memory system and a processor system that realize optimization of temporal locality and spatial locality of memory access. A memory system according to one aspect includes: a first memory having a memory capacity smaller than a second memory storing data of a second granularity, and storing data of a first granularity smaller than the second granularity; a part for reading data of a third granularity larger than the first granularity from the data stored in the second memory; and a data extracting part for extracting data of the third granularity read by the control part The data of the first granularity is stored in the first memory.

Description

[0001] This application is based on Japanese patent application 2016-164845 (filing date: August 25, 2016), and enjoys the priority of this application. The entire content of this application is incorporated by reference. technical field [0002] Embodiments of the invention relate to memory systems as well as processor systems. Background technique [0003] With the spread of big data processing, etc., the demand for high-speed memory access and low power consumption is increasing. The speed of memory access varies greatly depending on the structure of the cache memory. There is a property called temporal locality in which an address for which an access request has been made is highly likely to be accessed again. In addition, there is a property called spatial locality in which addresses in the vicinity of addresses that have had access requests are more likely to be accessed. Temporal locality and spatial locality are in a trade-off relationship. If temporal locality is...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0806G06F12/123
CPCG06F12/0806G06F12/123G06F12/04G06F3/0604G06F3/0631G06F3/0638G06F3/0652G06F3/0656G06F3/0685G06F12/0802G06F2212/60
Inventor 武田进藤田忍
Owner KIOXIA CORP
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