Single-ended negative feedback charge pump for delay-locked loop

Abstract

The invention relates to the field of integrated circuits, and can suppress a current mismatch problem and enhance output stability. The technical scheme of the invention is as follows: provided is asingle-ended negative feedback charge pump for a delay-locked loop, wherein sources of two PMOS transistors M1 and M2 are connected with a drain of a power supply vdd, a grid of the M2 is earthed, anda grid of the M1 is connected with a last output Vctrl; sources of PMOS transistors M5 and M6 are connected with a drain of the M1, grids of the M5 and M6 are connected, a grid voltage Vbias is 0.8V;drains of the M5 and M6 are connected with drains of NMOS transistors M3 and M4, and DN and UP signals are input into grids of the M3 and M4; sources of the M3 and M4 are connected and further connected to grids of NMOS transistors M12, M13 and M14; a grid and a drain of the M13 are connected with each other, drains of the M14 and M12 are connected with the drains of the M3 and M4. The single-ended negative feedback charge pump for the delay-locked loop provided by the invention is mainly applied to design and manufacture occasions of the integrated circuits.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to large-scale circuits using high-speed clocks, so as to meet the demand for accurate synchronization of internal clocks. Specifically, it relates to single-ended negative feedback charge pumps for delay-locked loops. Background technique [0002] The charge pump is an important part of the delay-locked loop, and the traditional analog delay-locked loop is shown in the description part of the drawing Figure 1 As shown, the reference clock obtains the phase delay through the voltage-controlled delay line and outputs it. The reference clock and the output clock are input to the frequency detector and phase detector at the same time. The UP and DN signals output by the frequency detector and phase detector are sent to the charge pump, and the output of the charge pump A capacitor C is attached to output voltage Vctrl, and Vctrl is input to the voltage-controlled delay line. The ro...

AI Technical Summary

Problems solved by technology

Because when the UP and DN signals are both high, the difference between the two current sources will charge and discharge the output node, causing Vctrl to change

Traditional single-ended charge pumps cannot suppress current source mismatch well

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