Heterojunction resistive switching memory and manufacturing method thereof
A technology of resistive memory and heterojunction, applied in electrical components and other directions, can solve the problems of difficulty in meeting high storage density, difficult practical application, complex process, etc., and achieve the effects of easy preparation, stable memristive behavior and low cost.
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Embodiment 1
[0041] See figure 1 , figure 1 It is a schematic diagram of a manufacturing method of a heterojunction resistive memory provided by an embodiment of the present invention. The method comprises the steps of:
[0042] Step a, preparing a semi-insulating substrate;
[0043] Step b, continuously growing an adhesion layer, a bottom electrode and Ga on the surface of the semi-insulating substrate 2 o 3 film;
[0044] Step c, using a spin coating process on the Ga 2 o 3 Growth of CH on the film surface 3 NH 3 PB 3 film;
[0045] Step d, in the CH 3 NH 3 PB 3 Dot-shaped top electrodes are grown on the surface of the film to form a heterojunction resistive variable memory.
[0046] Wherein, step a may include:
[0047] Growth of SiO on Si Substrate Surface by Thermal Oxidation Process 2 to prepare the semi-insulating substrate.
[0048] Further, after step a, it may also include:
[0049] The semi-insulating substrate was washed sequentially for 5 min with acetone sol...
Embodiment 2
[0067] See figure 2 , figure 2 It is a device schematic diagram of a heterojunction resistive memory provided by an embodiment of the present invention. The heterojunction resistive variable memory includes: a semi-insulating substrate 21, an adhesion layer 203, a bottom electrode 204, Ga 2 o 3 Film 205, CH 3 NH 3 PB 3 Thin film 206 and dot-like top electrode 207; Wherein, semi-insulating substrate 21 is made of Si substrate 201 and SiO produced by thermal oxidation on the surface of Si substrate 2 202, and the heterojunction resistive variable memory is prepared by the method described in the above embodiment.
[0068] Preferably, Ga 2 o 3 Thin film is N-type, CH 3 NH 3 PB 3 Thin film is P-type, N-type Ga 2 o 3 Thin films and P-type CH 3 NH 3 PB 3 The thin film forms a laminated PN heterojunction resistive layer.
[0069] The transistor of the present invention adopts CH 3 NH 3 PB 3 Provide a large number of electrons to the channel to form an n-type MO...
Embodiment 3
[0071] See Figure 3a ~ Figure 3f , Figure 3a ~ Figure 3f A process flow diagram of a heterojunction resistive memory provided by an embodiment of the present invention. This embodiment describes the technical solution of the present invention in detail on the basis of the above embodiments. Specifically, the method may include:
[0072] Step 1: Select a semi-insulating substrate.
[0073] Select Si substrate 301, and use thermal oxidation process to grow SiO on the surface of Si substrate 2 302 forms a semi-insulating substrate 31, SiO 2 The thickness of 302 is 80nm-120nm; the semi-insulating substrate 31 is cleaned to remove surface pollutants and natural oxide layer; the cleaning process is as follows: the semi-insulating substrate is placed in an acetone solution for ultrasonic cleaning for 5 minutes to remove surface pollutants, and then Ultrasonic cleaning with ethanol and deionized water for 5 min each, such as Figure 3a said;
[0074] Preferably, SiO 2 The ...
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