Chip embedded silicon substrate type fan-out type packaging structure and manufacturing method therefor

Abstract

The invention discloses a chip embedded silicon substrate type fan-out type packaging structure and a manufacturing method therefor. The packaging structure comprises a silicon substrate, wherein the silicon substrate has a first surface and a second surface; at least one groove A which extends to the second surface is formed in the first surface of the silicon substrate; at least one chip with an upward bonding pad surface is arranged in the groove A; the bonding pad surface of the chip is higher than the first surface of the silicon substrate for a certain distance; a thick adhesive layer which exposes the groove A and the chip is paved on the first surface; the sum of the thickness of the thick adhesive layer and the depth of the groove A is close to or equal to the thickness of the chip; and the electric power of the bonding pad of the chip is fan out to the upward side of the thick adhesive layer through a metal wiring layer. The thick adhesive layer is introduced to the surface of the silicon substrate, and the thick adhesive layer and the silicon substrate are jointly used as a chip fan-out carrier, so that requirement on the groove etching depth and the groove bottom etching uniformity in embedding the chip in the silicon substrate can be lowered, and the purposes of shortening etching process time on the silicon substrate, lowering etching and packaging costs and reducing warping degree are achieved.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a chip-embedded silicon-based fan-out packaging structure and a manufacturing method thereof. Background technique [0002] Fan-out wafer-level packaging technology currently uses a silicon base instead of a plastic encapsulant, and uses a silicon base instead of a molding compound as the fan-out base. , can accurately etch structures such as holes and grooves, and has good heat dissipation performance, but there are also certain shortcomings. In this way, the chip can be completely placed in the deep groove. However, when the silicon substrate is etched deeply, it is difficult to ensure the uniformity of the silicon substrate, and the etching cost and process of the silicon substrate are difficult. , wafer warpage is also large. Contents of the invention [0003] In order to solve the above-mentioned technical problems, the present invention proposes a chip-e...

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Problems solved by technology

[0002] Fan-out wafer-level packaging technology currently uses a silicon base instead of a plastic encapsulant, and uses a silicon base instead of a molding compound as the fan-out base. , can accurately etch structures such as holes and grooves, and has good heat dissipation performance, but there are also certain shortcomings. In this way, the chip can be completely placed in the deep groove. However, when the silicon substrate is etched deeply, it is difficult to ensure the uniformity of the silicon substrate, and the etching cost and process of the silicon substrate are difficult. , the wafer warpage is also large

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