Anti-emi super junction vdmos device structure and its preparation method

Abstract

The invention relates to an anti-EMI super-junction VDMOS device structure and a preparation method thereof. The method is characterized by carrying out boron ion implantation for three times at different inclination angles to form three P-type auxiliary depletion regions respectively after etching a deep trench in the process of preparing a super junction through a deep trench epitaxial filling technique, so that change of capacitance and Miller capacitance between a drain electrode and a source electrode caused at the moment a superjunction VDMOS is turned on or turned off can be slowed, and electronic system EMI characteristics are improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor power devices, and in particular relates to an anti-EMI super junction VDMOS device structure and a preparation method thereof. Background technique [0002] In applications such as high-voltage switching power supplies, vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS) with good body diode characteristics and high durability are required. However, conventional planar VDMOS devices have relatively high on-resistance, resulting in relatively high conduction losses in electronic systems. In the late 1990s, super-junction VDMOS devices designed based on the charge balance concept of the super-junction theory (Super-Junction) were introduced into the market. Compared with the conventional high-voltage planar VDMOS, the on-resistance Rsp per unit area of ​​the super-junction VDMOS is much smaller, so the super-junction VDMOS has a much smaller on-resistance Rds(...

AI Technical Summary

Problems solved by technology

The sharp change in the capacitance of the power device will cause a sharp change in the voltage or current on the drain and gate sides of the power device, which will be superimposed on the electronic circuit and cause EMI problems at the input and output ends of the circuit system.

[0004] With the advancement of deep trench epitaxial filling technology, the cell density of super junction VDMOS is getting higher and higher, the doping concentration of N-type epitaxial region is getting higher and higher, and the trench spacing is getting smaller and smaller. Reduce the on-resistance R ds(on) At the same time, it can meet the requirements of the breakdown voltage BV, and the trench depth is correspondingly deeper and deeper, but this also brings a problem that the deeper the trench, the more serious the EMI problem caused by power devices.

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