Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Vertical-channel SiC junction gate bipolar transistor and preparation method thereof

A bipolar transistor and junction gate technology, applied in the field of microelectronics, can solve the problems of complex structure, low production cost and yield, and reduce device mobility, so as to avoid the influence of device characteristics and reduce the difficulty of device technology Effect

Active Publication Date: 2017-05-24
XIDIAN UNIV
View PDF3 Cites 6 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The existence of the gate oxide layer introduces the influence of the interface state, which reduces the mobility of the device
The parasitic pnpn structure in the device is prone to latch-up effect in the high current state, and the device is no longer controlled by the gate
Relatively speaking, the structure of traditional IGBT devices is more complicated, and the production cost and yield are lower.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Vertical-channel SiC junction gate bipolar transistor and preparation method thereof
  • Vertical-channel SiC junction gate bipolar transistor and preparation method thereof
  • Vertical-channel SiC junction gate bipolar transistor and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0046] A SiC junction gate bipolar transistor device with a vertical channel, specifically as figure 2 As shown, including an N+ silicon carbide substrate 2, an emitter contact metal layer 1 formed on the surface of the N+ silicon carbide substrate 2, a P+ buffer layer 3 formed on the N+ silicon carbide substrate 2, and a P+ buffer layer 3 formed on the P-drift region 4, P+ collector region 8 formed on P-drift region 4, collector contact metal layer 9 formed on P+ collector region 8; also includes at least two P+ collector regions formed on P-drift region 4 a vertical trench, the bottom of the trench and the side walls of the trench are provided with an N-type gate region 7, the N-type gate region 7 at the bottom of the trench is implanted with a gate N+ implantation region 5, and the gate N+ implantation region 5 is formed with a The gate is in contact with the metal layer 6 ; the N-type gate region 7 is in contact with the P+ collector region 8 .

[0047] Among them, the e...

Embodiment 2

[0075] A SiC junction gate bipolar transistor device with a vertical channel, specifically as figure 2 As shown, including an N+ silicon carbide substrate 2, an emitter contact metal layer 1 formed on the surface of the N+ silicon carbide substrate 2, a P+ buffer layer 3 formed on the N+ silicon carbide substrate 2, and a P+ buffer layer 3 formed on the P-drift region 4, P+ collector region 8 formed on P-drift region 4, collector contact metal layer 9 formed on P+ collector region 8; also includes at least two P+ collector regions formed on P-drift region 4 a vertical trench, the bottom of the trench and the side walls of the trench are provided with an N-type gate region 7, the N-type gate region 7 at the bottom of the trench is implanted with a gate N+ implantation region 5, and the gate N+ implantation region 5 is formed with a The gate is in contact with the metal layer 6 ; the N-type gate region 7 is in contact with the P+ collector region 8 .

[0076] Among them, the e...

Embodiment 3

[0104] A SiC junction gate bipolar transistor device with a vertical channel, specifically as figure 2 As shown, including an N+ silicon carbide substrate 2, an emitter contact metal layer 1 formed on the surface of the N+ silicon carbide substrate 2, a P+ buffer layer 3 formed on the N+ silicon carbide substrate 2, and a P+ buffer layer 3 formed on the P-drift region 4, P+ collector region 8 formed on P-drift region 4, collector contact metal layer 9 formed on P+ collector region 8; also includes at least two P+ collector regions formed on P-drift region 4 a vertical trench, the bottom of the trench and the side walls of the trench are provided with an N-type gate region 7, the N-type gate region 7 at the bottom of the trench is implanted with a gate N+ implantation region 5, and the gate N+ implantation region 5 is formed with a The gate is in contact with the metal layer 6 ; the N-type gate region 7 is in contact with the P+ collector region 8 .

[0105] Among them, the e...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
widthaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention provides a vertical-channel SiC junction gate bipolar transistor and a preparation method, mainly solves a problem of interface states brought about by an oxide layer of a SiC IGBT (Insulated Gate Bipolar Transistor) device in the prior art, avoids a possibly occurring latch-up effect, reduces processing steps and saves the processing cost at the same time. The characteristics are that a channel structure of a vertical-channel JFET (Junction Field-Effect Transistor) is adopted in a P- drift region to replace an upper structure of the traditional IGBT device, and the width of a channel region of the device is 1-4 microns. The vertical-channel SiC junction gate bipolar transistor provided by the invention has the advantages of simple production process, low cost, high current gain and the like, and can be applied to a stabilized switching power supply, electric energy conversion, automobile electronics, oil drilling equipment and the like.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and relates to a semiconductor device, in particular to a silicon carbide bipolar transistor based on a vertical channel junction gate and a preparation method thereof. Background technique [0002] With the rapid development of power electronics technology, the demand for high-power semiconductor devices is becoming more and more significant. Due to the limitation of materials, the characteristics of traditional silicon devices have reached its theoretical limit. Silicon carbide is a wide bandgap semiconductor material that has been developed rapidly in the past ten years. It has wide bandgap, high thermal conductivity, and high carrier saturation migration. High efficiency, high power density and other advantages, can be applied to high power, high temperature and radiation resistance and other application fields. Among them, IGBT (silicon carbide insulated gate bipolar transistor) is ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/739H01L21/04
CPCH01L21/0445H01L29/66068H01L29/7395
Inventor 宋庆文刘思成汤晓燕元磊张艺蒙张玉明
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com