A phase-change memory readout circuit and readout method

Abstract

The invention provides a readout circuit and a readout method of a phase change memory. The readout circuit includes a read reference voltage generation circuit which generates a read reference current that can quickly distinguish a read crystalline resistor current and a read amorphous resistor current, and converts the current signal into a voltage signal; and a sensitive amplifier which reduces the read reference voltage into the read reference current and compares the read reference current with the current red from a phase change memory unit. The readout circuit can obtain the read current and the read reference current at the same time, wherein the transient value of the read reference current is between the read crystalline resistor current and the read amorphous resistor current. In the invention, matching to bit line parasitic parameter and read transmission gate parasitic parameter is introduced into the read reference current, while matching to current mirror parasitic parameter is introduced into the read current, thereby eliminating false-reading phenomenon and reducing readout time. The readout circuit has high signal transmission speed, wide available range and simple parasitic parameter matching method.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a phase-change memory readout circuit and a readout method. Background technique [0002] In the field of integrated circuit manufacturing, as the process nodes continue to shrink, traditional charge-based memories are increasingly restricted. Various new memories and new structures have been invented to break through the original limits: MLC NAND, MLCNOR, TLC NAND, MRAM, RRAM, FeRAM, 3D-Xpoint, 3D-NAND, etc. The read latency of traditional and new memories is different: for SRAM as memory, the read time of DRAM is within 10ns, that of NAND Flash is around 50us, that of 3D-NAND is around 500us, and that of hard disk is around 10ms. If the read time of the memory can be further mined, its competitiveness will be greatly improved. [0003] Phase Change Memory (Phase Change Memory, PCM) is a memory based on the Ovshinsky electronic effect proposed by Ovshinsky in the l...

AI Technical Summary

Problems solved by technology

The above-mentioned read destruction phenomenon requires that the bit line voltage must be low enough during the read process, thereby limiting the difference between the high-resistance state and the low-resistance state bit line voltage, thereby limiting the read speed of the phase change memory and reducing the read data rate. reliability

[0007] Second, the limitation of parasitic effects

[0009] Therefore, how to improve the above-mentioned long reading time and how to improve the speed characteristics of the phase change memory has become a technical problem to be solved urgently by those skilled in the art.

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