A FPGA implementation system and method for oversampling data clock recovery

Abstract

The invention discloses an oversampling data clock recovery FPGA realizing system and method; the system comprises a differential signal conversion module arranged in the FPGA, a programmable input delay unit, an input serial-parallel conversion module and a fixed mode clock management module; the differential signal conversion module is connected with the programmable input delay unit; the programmable input delay unit is connected with the input serial-parallel conversion module; the input serial-parallel conversion module is connected with the fixedly mode clock management module. The differential signal conversion module carries out caching treatment for an external input differential signal sent into the FPGA, thus forming two FPGA internal differential signals; aiming at the problems that the FPGA chip cannot provide sufficient GE port special pins, the novel method can use a normal IO to realize data clock recovery; the method uses normal IO to carry out data recovery, thus flexibly satisfying various demands, and the realizing number can no longer be limited by special pins carried by the FPGA chip.

Description

technical field [0001] The invention relates to the relevant technical field of serial data recovery of a GE port in an FPGA chip on a communication device, and specifically relates to an FPGA implementation system and method for oversampling data clock recovery. Background technique [0002] At present, the data recovery of the GE interface on the FPGA chip firstly needs to send a reference clock to the processing module, and then use the reference clock to combine with the received serial data to recover the clock of the data sent by the peer end, and then upload the recovered clock to the After the global clock network, collect data and perform serial-to-parallel conversion. [0003] This function is put into the FPGA chip through the hard core IP, and correspondingly has dedicated pins. The number of dedicated pins supported by different chip models is also different. When the number of interfaces is required to be large, some high-end chips should be selected. Because ...

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Problems solved by technology

[0004] The purpose of the present invention is to provide an FPGA implementation system and method for oversampling data clock recovery, aiming at the problem that sufficient GE port dedicated pins cannot be provided on the FPGA chip, a method that can also realize data clock recovery through ordinary IO is designed ;Using ordinary IO for data recovery can flexibly meet various needs, and the number of implementations is no longer limited to the dedicated pins that come with the chip

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