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Method for improving memory reliability through fault isolation technology

A fault isolation and reliability technology, applied in static memory, instruments, etc., can solve problems such as system downtime, achieve the effect of preventing downtime, reducing the risk of system downtime, and improving product competitiveness

Inactive Publication Date: 2016-09-28
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Due to the evolution of the production process, more and more defects appear in the DRAM manufacturing process, and the yield rate is also declining. Although traditional DRAM manufacturers can screen out good particles through ATE and other testing methods in the manufacturing process, but at the end-user end The problem of system downtime caused by DRAM Cell failure over time cannot be avoided

Method used

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  • Method for improving memory reliability through fault isolation technology
  • Method for improving memory reliability through fault isolation technology

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Embodiment 1

[0021] Such as figure 2 As shown, a method for improving memory reliability through fault isolation technology, said method dynamically adds the Cell address information that is about to go bad during use to the "failure address list" through the test program after the DRAM particles leave the factory In the middle, let the memory controller not access the address space of this piece, thereby prolonging the service life of the memory system, and the economic benefit is obvious.

Embodiment 2

[0023] On the basis of Embodiment 1, the test program described in this embodiment tests all the basic storage cells (Cells) in the DRAM through Refresh refresh charge and discharge, Leakage leakage and other test programs to find out the basic storage cells (Cells) with relatively weak charge retention time ( Cell) to monitor and record the number of errors. When a basic storage unit (Cell) reaches a certain threshold, these error addresses will be marked and isolated to prevent the operating system (OS) from ) to access, so as to achieve the purpose of improving the reliability of the memory system, reduce the risk of system downtime due to memory failure, and have obvious economic benefits.

Embodiment 3

[0025] On the basis of embodiment 2, the method test steps described in the present embodiment are as follows:

[0026] 1) Extend the refresh time of the basic storage unit (Cell), which is longer than the 64ms charge retention time specified in the JEDEC standard, and extend its refresh cycle > 64ms through the memory controller, and those relatively weak cells are in the capacitor after 64ms The charge will leak faster, making it easier to find weaker cell units;

[0027] 2) According to the arrangement order of cells inside the DRAM, by designing a special test mode pattern: set a certain basic storage unit (Cell) to 1, and the surrounding six basic storage units (Cell) to 0, use cell to cell The principle of leakage to find out the weaker cell unit;

[0028] 3) Monitor the problematic basic storage unit (Weak Cell unit) found in the above two tests, and count the number and probability of its long-term error, so as to determine whether it is a random error or a persistent...

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Abstract

The invention discloses a method for improving memory reliability through fault isolation technology. The method uses a test program to dynamically add Cell address information that is about to deteriorate during use to the "failure address list" after DRAM particles leave the factory. In ", let the memory controller not access this address space, thereby prolonging the service life of the memory system. The method of the invention can achieve the purpose of improving the reliability of the memory system, reduce the risk of system downtime due to memory failure, reduce the failure caused by memory, improve product competitiveness, and have obvious economic benefits.

Description

technical field [0001] The invention relates to the technical field of computer system storage design, in particular to a method for improving memory reliability through fault isolation technology. Background technique [0002] All programs in the computer run in the memory, which is used to temporarily store the calculation data in the CPU and the data exchanged with external memories such as hard disks. As the DRAM process advances from 30nm to 14nm, the unit density continues to increase, and a single 4Gb, 8Gb or even larger capacity particle has become the mainstream. Because the volume of each cell (basic storage unit) is getting smaller and smaller, its ability to hold charges will become weaker, and the characteristics of some cells will gradually deteriorate as the usage time increases. [0003] DRAM Cell consists of a transistor (Transistor) and a capacitor (Capacitor). The capacitor can store a certain amount of charge. A charged capacitor is considered a logical ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/00G11C29/44
CPCG11C29/44G11C29/88
Inventor 贡维李鹏翀林楷智
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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