PSM mode adaptive voltage regulator based on output voltage segmentation

Abstract

The invention discloses a PSM mode adaptive voltage regulator based on output voltage segmentation, and aims to provide a voltage regulator which is good in transient response characteristics and high in power conversion efficiency under light load and can effectively reduce power consumption of the CPU of a load processor. According to the technical scheme, a clock signal generator generates three clock signals including a load processor clock, a delay line resetting signal and a delay testing signal according to a control signal requested by an external CPU; compared with a rising edge of the delay testing signal, a rising edge of the delay line resetting signal is lagged by a clock period TS of the load processor clock signal; and when a testing signal in the TS is transmitted to a data input end of a trigger D2, the CPU of the load processor judges whether output voltage of a power converter can enable a key path of the CPU to work normally or not according to the transmission condition of the delay testing signal in a delay line, output voltage of the power converter is adjusted according to the detected result, and CPU delay is adaptively adjusted to be L / (L+ deltaL) times of the TS.

Description

technical field [0001] The invention belongs to the technical field of power electronics and is used for self-adaptive on-line adjustment of power supply voltage with digital control function for processor (CPU or DSP) load. Background technique [0002] With the improvement of integrated circuit integration, the power density of integrated circuits is increasing, the power consumption of processors is as high as more than 100 watts, and the radiator is bulky and expensive. At the same time, the development speed of battery technology lags far behind the demand for electric energy of integrated circuits, which has become an important factor restricting the development of integrated circuits. Many complex electronic components, such as central processing unit CPU and digital signal processor DSP, can work at different clock frequencies. In digital circuits with high-frequency operation, the switching power consumption of the gate circuit is the main component of power consum...

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Problems solved by technology

[0004] 1) Mukti Barai and others used ADC, DPID, and DPWM to form a control loop to make an adaptive DC-DC converter (see the document "Dual-Mode Multiple-Band Digital Controller for High-Frequency DC-DC Converter", Power Electronics, IEEE Transactions on Volume 24, Issue 3, March 2009Page(s):752-766), but this method requires digital loop compensation

However, digital loop compensation usually needs to obtain compensation parameters through modeling, and the parameters obtained by modeling cannot be very accurate, which will inevitably lead to more or less oscillation in the compensation loop, and eventually lead to unstable output voltage

[0005] 2) Shidhartha Das and others adjust the voltage according to the operating error rate of the load circuit CPU or DSP during the voltage adjustment process, and at the same time use the error correction mechanism to correct the error to achieve adaptive voltage adjustment (see the document "RazorII: In SituError Detection and Correction for PVT and SER Tolerance”, Solid-State Circuits, IEEE Journal of Volume 44, Issue 1, Jan. 2009 Page(s): 32-48), but this method is complex to implement, and system error correction takes time

[0006] 3) Dae Woon Kang et al. designed an all-digital adaptive Buck power converter that does not require proportional, integral and differential PID compensation based on a finite state machine (see the document "A High-Efficiency Fully Digital Synchronous BuckConverter Power Delivery System Based on a Finite-State Machine", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 14, Issue 3, March 2006 Page (s): 229-240), but its circuit implementation is more complicated than the method described in the present invention

Chinese patent application number CN101995895B, 2012.06.13, discloses an adaptive voltage regulator based on PSM modulation mode, which is an adaptive voltage regulator based on PSM mode by Zhen Shaowei et al. conduction) The duty cycle is limited by the minimum value of the output voltage, and the transient response capability of the output voltage upward regulation is poor

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