Frequency adjusting method, system on chip, and terminal

Abstract

Embodiments of the invention provide a frequency adjusting method, a system on a chip, and a terminal. According to the embodiments, when access bandwidth demands on a DDR memory change, a first frequency adjustment request for a DDR interface is generated through a CPU to adjust the operating frequency of the DDR interface; and since the operating frequency of the DDR interface is gradually adjusted according to a predetermined adjustment amount of the frequency adjustment coefficient of a spread spectrum clock generator in each adjustment and interval time between two adjacent adjustment, phase-locked loops of DLL and the spread spectrum clock generator in DDR are prevented from loss of lock, so the DDR memory can also be accessed during frequency adjustment of the DDR interface and system performance is guaranteed.

Description

technical field [0001] The present application relates to the technical field of DDR frequency processing, in particular to a method for adjusting frequency, a system on chip and a terminal. Background technique [0002] At present, mobile terminals generally use Double Data Rate Synchronous Dynamic Random Access Memory (English full name: Double Data Rate Synchronous Dynamic Random Access Memory, English abbreviation: DDR SDRAM) as its memory, and DDR SDRAM is generally referred to as DDR. It changes, which changes with the change of the operating frequency of the central processing unit. [0003] figure 1 Shown is a structural diagram of a system-on-a-chip (SoC) including a DDR interface combined with a DDR memory. The SoC system includes a central processing unit CPU, a service processor, and a phase-locked loop (English full name: Phase -Locked Loop, English abbreviation: PLL), DDR controller and DDR interface, among them, DDR controller, DDR interface (also known as D...

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Problems solved by technology

[0014] In the above solution, during the frequency adjustment period of the DDR interface, that is, during phase 2, the access operation of the DDR memory needs to be suspended, and the read and write accesses of the service processor and the CPU will be suspended. At this time, the internal cache of the service processor needs to be increased to To ensure business continuity, take a DDR3 64Bit DDR interface as an example. When the system needs to reduce power consumption from 1600Mpbs to 1200Mpbs, if the above method is used, the time for the entire DDR memory to suspend access needs to be at least 50uS (actually each system DDR There are differences in parameters, 50us is a conservative estimate, many systems will exceed 50us), during this period, all online business processors (such as network, video input and display) need to consider increasing the cache to save the data that needs to be received or sent on the DDR interface in real time, Assuming that the efficiency of DDR is 60%, then during the suspension of DDR access, the total amount of data that needs to be cached in the internal cache of the service module is: 1200*32*50*0.6 / 1000000~=3Mbit, which requires a relatively high cache in the service processor. In addition, during the frequency adjustment of the DDR interface, the CPU cannot access the DDR memory, which affects the processing performance of the CPU.

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