Chip structure and fabrication method thereof

Abstract

The invention provides a chip structure and a manufacturing method thereof. According to the invention, a welding pad is formed on a cutting channel at one side of a first direction of a chip and is connected with the chip through a metal connecting wire, a test probe is pricked into the welding pad located at the cutting channel when a CP test is carried out subsequently, and no damage is imposed on the chip, so that the quality of the chip can be ensured, and the number of available chips of a wafer is increased. In addition, subsequent cutting for the chip structure is not affected after the CP test is completed. Furthermore, the invention provides a manufacturing method of the chip structure. A photomask unit on the cutting channel at the other side of the first direction of the chip is set to be a dark portion, thereby avoiding secondary exposure for the public cutting channel, ensuring the performance of the welding pad on the public cutting channel, and enabling the CP test to be carried out smoothly.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a chip structure and a manufacturing method thereof. Background technique [0002] In semiconductor manufacturing, each wafer is composed of several chips, and a scribe lane is provided between the chips. The scribe lane has two functions: [0003] 1) Place the test structure (test key) for wafer acceptability (WAT) and reliability (RE), which is used to monitor electrical parameters and reliability, as well as alignment marks for some measurements of the lithography process ); [0004] 2) Used as a cutting tape during package testing. [0005] Please refer to figure 1 , figure 1 It is a schematic diagram of the chip structure 10 under a photomask unit (Shot) on the wafer; when the wafer is exposed to photoresist, it usually exposes a chip structure 10 according to a single photomask unit, and the chip structure under a single photomask unit 10 usually includes sev...

AI Technical Summary

Problems solved by technology

And as we all know, when carrying out CP test, it is very easy to damage the bonding pad 12, so that part of the effective area in the chip 11 loses its effect, reduces the number of useful chips 11, and affects the improvement of the production efficiency; and, because the chip structure 10 shares The dicing lane 14 cannot be utilized, and it occupies the area of ​​the wafer, which is not conducive to improving the utilization rate of the wafer

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