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Pipeline architecture-based low-latency FAST quotation decoding device and method

A pipelined, low-latency technology, applied in the field of information, can solve the problem of not realizing parallel decoding of FAST market information, and achieve the effect of simplifying control and update logic, good scalability, and improved performance

Active Publication Date: 2016-06-08
INST OF INFORMATION ENG CAS
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AI Technical Summary

Problems solved by technology

Data dependencies of FAST messages limit parallel decoding of FAST quotes
The published literature has not yet realized the work of parallel decoding of FAST market information

Method used

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  • Pipeline architecture-based low-latency FAST quotation decoding device and method

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Embodiment Construction

[0031] In order to make the above objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described below through specific embodiments and accompanying drawings.

[0032] In the present invention, special hardware is used to accelerate the decoding of FAST market data, such as FPGA (Field Programmable Gate Array, Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit, application specific integrated circuit) and the like.

[0033] First of all, the FAST market decoding processor based on the bus architecture is designed. For a specific FAST market template, first connect the decoders (also called decoding operators) of each field defined in the template to the internal bus of the decoding processor. The internal bus is divided into two types: data bus and control bus. Under the control of the decoding controller, the decoding of each field is completed in turn.

[0034] After that...

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Abstract

The invention relates to a pipeline architecture-based low-latency FAST quotation decoding device and method. The device comprises internal buses, a controller, and field decoding operators in each of all the fields of FAST quotation data. The field decoding operators are respectively connected with the internal buses. Under the control of the controller, each filed of the FAST quotation data can be successively decoded. The internal buses are composed of a data bus and a control bus. By means of the data bus, the FAST quotation data are inputted into a stream buffer and the data transmission between the field decoding operators and an FIX message buffer is enabled. The control bus is responsible for the decoding operation of each field. The field decoding operators are in the form of three-stage decoding operators. Meanwhile, the streamlined type FAST quotation decoding process is realized based on the bus connection. According to the technical scheme of the invention, the quotation decoding speed is effectively accelerated. Meanwhile, the invention provides a support for the financial applications of algorithmic trading, high-frequency trading, market risk monitoring and the like.

Description

technical field [0001] The invention belongs to the field of information technology, and in particular relates to a low-latency FAST market decoding device and method based on a pipeline architecture. Background technique [0002] Financial exchanges release the latest market data (marketdata) to market participants in real time in the form of multicast. Market data includes the latest buying and selling quotations and demand, transaction records of financial products (such as opening price, highest price, lowest price, current price, transaction volume, transaction value, etc.), order status and other latest information. Financial participants analyze the incoming financial market data in real time through software such as market-watching software or algorithmic trading, and make financial transaction decisions (such as buying and selling financial products) based on the latest market conditions. Therefore, timely analysis of financial market data is crucial for market par...

Claims

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Application Information

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IPC IPC(8): G06Q40/04G06F13/40
CPCG06F13/4068G06F2213/0038G06Q40/04
Inventor 姜磊唐球戴琼苏马静杨嘉佳白旭
Owner INST OF INFORMATION ENG CAS
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