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Gate structure forming method and gate structure

A gate structure and gate technology, which is applied in the direction of electrical components, circuits, semiconductor devices, etc., can solve the problem of reduced electrical reliability of the gate dielectric layer, decreased electrical reliability of the gate structure, and increased leakage probability of the gate dielectric layer and other issues, to achieve the effect of increasing electrical stability, reducing the probability of leakage, and reducing the size of MOS devices

Inactive Publication Date: 2016-04-27
SEMICON MFG INT (SHANGHAI) CORP
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, when the thickness of the gate dielectric layer is reduced to a certain extent, the leakage probability of the gate dielectric layer will increase significantly, and the electrical reliability of the gate dielectric layer will also decrease.
[0003] Taking complementary metal-oxide-semiconductor devices (MOS) as an example, when the gate dielectric layer in the MOS device is thinned to a certain extent, the electrical reliability of the gate structure will decrease, which will affect the reliability of the MOS device.

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  • Gate structure forming method and gate structure
  • Gate structure forming method and gate structure

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Embodiment Construction

[0047] Taking a semiconductor device including an input / output MOS device and a core MOS device as an example, the voltage value required by the input / output MOS device is generally relatively high, that is to say, the thickness of the gate dielectric layer of the input / output MOS device needs to be adjusted. Larger, but this is not conducive to reducing the EOT size of the input / output MOS device, because the usual way to reduce the EOT size is to reduce the physical thickness of the gate dielectric layer, but doing so will cause leakage of the gate dielectric layer and electrical reliability The performance is reduced, which in turn leads to the reduction of the electrical performance of the input / output MOS device.

[0048] Therefore, the present invention provides a method for forming a gate structure, comprising the following steps:

[0049] providing a substrate, the substrate including a first region for forming an input / output MOS device and a second region for forming...

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Abstract

The invention provides a gate structure forming method and a gate structure. The gate structure forming method comprises the steps of: providing a substrate; forming a first oxidation layer; forming a nitride layer; forming a first gate, so that the first oxidation layer and the nitride layer positioned in a first region form a gate dielectric layer of an input / output MOS device; and forming a second gate on a substrate in a second region. The gate structure comprises a substrate, a first oxidation layer positioned on the substrate in the first region, the nitride layer positioned on the surface of the first oxidation layer, the first gate positioned on the nitride layer in the first region, and the second gate positioned on the substrate in the second region, wherein the nitride layer is formed by carrying out nitrogen treatment on the first oxidation layer. The gate structure forming method and the gate structure have the beneficial effects of reducing probability of electric leakage of the gate dielectric layer, increasing electrical stability of the gate dielectric layer, and reducing thickness of the equivalent oxidation layer under the condition that the physical thickness of the gate dielectric layer of the input / output MOS device is unchanged.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a gate structure and the gate structure. Background technique [0002] In today's market, the integration density of integrated circuits is becoming higher and higher, and the size of semiconductor devices needs to become smaller and smaller. Correspondingly, the equivalent oxide thickness (Effective Oxide Thickness, EOT) of the gate dielectric layer as a part of semiconductor devices is also increasing. need to be reduced proportionally. However, when the thickness of the gate dielectric layer is reduced to a certain extent, the leakage probability of the gate dielectric layer will obviously increase, and the electrical reliability of the gate dielectric layer will also decrease. [0003] Taking a complementary metal-oxide-semiconductor device (MOS) as an example, when the gate dielectric layer in the MOS device is thinned to a certain extent, the...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L29/423H01L29/51
Inventor 何有丰
Owner SEMICON MFG INT (SHANGHAI) CORP
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