A hybrid memory hardware implementation system and method

Abstract

The invention relates to the field of a memorizer, and in particular to a hardware implementation system and method for a hybrid memory. The hybrid memory at least comprises N DRAM memorizers, at least an NCM memorizer, an address lookup conversion module, a control module and a multiplexer, wherein the N DRAM memorizers are divided into a main distributing region and a tail end distributing region according to DRAM storage unit retention time; N is an integer; the at least one NCM memorizer can substitute the DRAM memorizers to store the storage data in the tail end distributing region of the DRAM memorizers; the address information of the storage data in the tail end distributing region in the DRAM memorizers and the corresponding address information in the NCM memorizer for substituting the DRAM memorizers to store the storage data in the tail end distributing region in the DRAM memorizers are pre-stored in the address lookup conversion module; the control module is used for obtaining address information and address mapping relation, and judging the output access source of the system data according to the address information and address mapping relation, and the control module generates and outputs a control signal according to the source of the output access; and the multiplexer is connected with the control module, the DRAM memorizers and the NCM memorizer separately for receiving the control signal and selecting data for outputting according to the control signal.

Description

technical field [0001] The invention relates to the field of memory, in particular to a hardware implementation system and method of a hybrid memory. Background technique [0002] In the past few decades, the cost of DRAM (Dynamic Random Access Memory, DRAM) has been continuously reduced along with Moore's Law. However, as the feature size becomes smaller and smaller, the chip has higher and higher requirements for power consumption. Due to the leakage of DRAM storage capacitors, it must be refreshed every once in a while, and the refresh power consumption is getting larger and larger. figure 1 It is a schematic diagram of the proportion and trend of DRAM refresh power consumption in the prior art, such as figure 1 As shown, the DRAM refresh power consumption further increases with the increase of the DRAM capacity. The refresh cycle of a DRAM is determined by the retention time of charges in its memory cells. [0003] Figure 2a-2b It is a schematic diagram of DRAM rete...

AI Technical Summary

Problems solved by technology

It can be seen from the figure that the holding time of most storage units can reach 1s or even longer, while less than 1% of the storage units are distributed at the tail end, and their holding time is lower than 1s or even less than 100ms

[0005] There are still many problems unsolved in this technical solution. For example, when the memory controller requests data from the hybrid memory, it sends an address to the hybrid memory. How does the hybrid memory determine whether the data corresponding to the address is stored in the NCM or in the NCM? In DRAM, how the physical address of NCM and the physical address of DRAM are mapped, this is the technical loophole of adding NCM storage

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