A low power consumption digital accelerometer interface circuit system

Abstract

The invention belongs to the field of MEMS inertial devices, and in particular relates to a low-power consumption digital accelerometer interface circuit system. The invention includes a driving signal generating part, a charge integrator, a precompensator, a sample and hold circuit, a third-order ΣΔ modulator and a 1-bit electrostatic force feedback. The four parts do not need to work at high frequency, but only need to work at lower frequency, which can greatly reduce the power consumption of charging and discharging mechanical capacitance and parasitic capacitance. The operational amplifier in the third-order electrical ΣΔ modulator is replaced by an inverter. Since the inverter can provide a wide unity-gain bandwidth at extremely low quiescent current, although the 105 has a high operating frequency, its Power consumption is greatly reduced.

Description

technical field [0001] The invention belongs to the field of MEMS inertial devices, and in particular relates to a low-power consumption digital accelerometer interface circuit system. Background technique [0002] High-precision micro-mechanical MEMS (Micro Electromechanical System) accelerometers are widely used in aerospace, automotive, biomedicine, environmental monitoring and other fields due to their advantages of miniaturization, intelligence, integration, and high reliability. Typical applications MEMS accelerometer designs in these areas focus on noise characteristics, bias stability, and DC accuracy. However, according to market analysis, consumer electronics is still the largest application field of MESM accelerometers. In such applications, in addition to the above requirements, the accelerometer must also have the characteristics of low power consumption and digital output. Sigma-Delta (ΣΔ) modulation technology is an important way to realize analog-to-digital ...

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Problems solved by technology

[0003] At present, there have been a lot of reports on the capacitive accelerometer interface circuit using the ΣΔ modulation structure. However, there is an important problem in these circuits that the power consumption is too large. There are two reasons: first, in order to reduce the quantization noise of the system, improve Oversampling rate, the whole system works at a very high sampling frequency, however, too high sampling frequency causes very large mechanical capacitance and parasitic capacitance to be charged and discharged at the same frequency, which leads to high power consumption

Second, although a sensitive unit with second-order low-pass characteristics can be used as an integrator in a ΣΔ modulator, the system has a very low signal-to-quantization-noise ratio (SQNR) due to its very low DC gain. In order to improve the SQNR, It is necessary to cascade several electrical integrators after the sensitive unit, which also operate at high frequencies, and the operational amplifiers in them also consume a lot of power

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