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System level optimization method for power supply voltage of SOI process

A technology of power supply and optimization method, which is applied in the fields of electrical digital data processing, instruments, calculations, etc., can solve problems such as circuit performance weakening, and achieve the effect of maximizing circuit performance and minimizing circuit power consumption

Inactive Publication Date: 2015-11-25
SHANGHAI RES INST OF MICROELECTRONICS SHRIME PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, The reduction will directly lead to the weakening of the circuit performance

Method used

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  • System level optimization method for power supply voltage of SOI process
  • System level optimization method for power supply voltage of SOI process
  • System level optimization method for power supply voltage of SOI process

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Embodiment Construction

[0029] The technical solution of the present invention will be further described below in conjunction with the drawings and specific embodiments.

[0030] figure 1 This is a flowchart of a system-level optimization method for SOI process-oriented power supply voltage proposed by an embodiment of the present invention. With reference to the figure, the specific steps of the embodiment of the present invention are as follows:

[0031] (1) Establish as figure 2 Thermal model of the chip shown:

[0032]

[0033] It can be estimated from the substrate temperature and total power consumption of a specific chip in the same package.

[0034] for ,among them Is the thickness of the buried oxide layer, Is the thermal conductivity of the buried oxide layer, and A is the area where the transistor generates power.

[0035] (2) Definition

[0036] (3) Definition with Analytical model

[0037] (4) Different with SPICE with Under the bias conditions, simulate a image 3 The time delay of the...

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Abstract

The invention provides a system level optimization method for a power supply voltage of an SOI process, which is used for optimizing the power supply voltage of a circuit chip based on the SOI process at the early design stage with a heat effect considered. The main steps comprise: establishing a thermal model of the chip; establishing a total power consumption model of the chip; establishing a function expression with the power consumption and a temperature as independent variables; establishing an autocorrelation equation based on the thermal model; establishing a time delay model of temperature consciousness; defining an optimization function of time delay and power consumption; and calculating a minimum value of FOM to figure out an optimal value. The system level optimization method provided by the invention has the beneficial effects that, the influence of temperature on the power consumption of the chip and the circuit performance in the SOI process is considered, and on this basis, the power supply voltage is optimized in a system level to maximize the circuit performance and minimize the circuit power consumption. The value of the optimization method is to quantitatively see the optimization result as soon as possible to help the early architecture of a designer.

Description

Technical field [0001] The invention relates to the technical field of integrated circuit computer-aided design, in particular to a system-level optimization method of power supply voltage under SOI technology. Background technique [0002] With the gradual shrinking of the feature size of VLSI to advanced nanotechnology nodes, a series of new problems have emerged in bulk silicon technology in terms of materials, device structures, and manufacturing processes. In order to overcome the shortcomings of bulk silicon CMOS technology, SOI technology has been proposed and has gradually become the mainstream technology for manufacturing high-speed, low-power, and highly integrated VLSI. [0003] Although SOI technology has many incomparable advantages over bulk silicon technology, the main feature of SOI technology comes from full dielectric isolation (SOICMOS devices also contain a layer of SiO 2 It is the insulating oxide buried layer of the material), and the thermal conductivity of t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 张炯蒋乐乐徐帆程玉华
Owner SHANGHAI RES INST OF MICROELECTRONICS SHRIME PEKING UNIV
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