Wafer-level chip packaging method

Abstract

The invention relates to the field of the fabrication of a semiconductor device, in particular to a wafer-level chip package method. The wafer-level chip package method comprises the following steps of: arranging a bonding material on the supper surface of a first wafer and the upper surface of a second wafer; carrying out a planarization process on the bonding material; and finally, carrying out a grinding process on the edges of the first wafer and the second wafer to reduce the edge stress of the wafers so as to make warping degrees lower and make no crack at a bonding position of the first wafer and the second wafer. By changing the sequences of planarization and grinding, the edge warping degrees of the wafers are reduced so as to improve the wafer quality.

Description

technical field [0001] The invention relates to the field of semiconductor device preparation, in particular to a wafer-level chip packaging method. Background technique [0002] Wafer-level chip packaging technology is a technology that performs packaging and testing on the entire wafer and then etches a single finished chip. The size of the packaged chip is the same as that of the bare chip. [0003] The difference between wafer-level chip packaging technology and traditional packaging methods is that traditional chip packaging is etched first and then packaged and tested, and after packaging, the size of the original chip is increased by about 20%; Packaging and testing are carried out on the wafer before scribing and dividing. Therefore, the volume after packaging is almost the same as the size of the IC bare chip, which can greatly reduce the size of the IC after packaging. [0004] At present, with the requirement of wafer assembly thickness, the thickness of chip pac...

AI Technical Summary

Problems solved by technology

[0004] At present, with the requirement of wafer assembly thickness, the chip packaging thickness is required to be as thin as possible. When the chip size is small to a certain range, such as less than 600 microns, the thickness of the surface mount process will be more difficult.

At the same time, because silicon is relatively brittle after etching, it is easier to cause problems such as chip chipping and chipping when sucking it directly with a suction nozzle.

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