Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A memory wafer testing method and memory testing machine

A memory testing and wafer testing technology, applied in the field of memory wafer testing methods and memory testing machines, can solve the problems of damaged testers, damaged probe cards, etc., so as to save testing cost and time, and avoid large The effect of leakage current damage

Active Publication Date: 2018-03-30
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the process of using a tester with a high number of simultaneous measurements for wafer probe testing, all the DUTs for the same test are usually powered on at the same time, which can easily lead to excessive wafer leakage of failed chips and damage the probe card of the tester. The root cause of this phenomenon is: during the test process using the high-quality testing machine (KALOS testing machine of the 768 testing machine), since the test channel does not have a power protection circuit, the machine uses the test channel to send power to the wafer. The maximum current of the test power supply provided by the DUT cannot exceed 10mA, and the leakage current in the central area of ​​the leakage wafer will be as high as 45mA (the current of a normal wafer is below 1mA). This ultra-high leakage current will flood into the test channel and eventually damage the test. machine probe card

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A memory wafer testing method and memory testing machine
  • A memory wafer testing method and memory testing machine
  • A memory wafer testing method and memory testing machine

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] In order to make the purpose and features of the present invention more obvious and understandable, the specific implementation of the present invention will be further described below in conjunction with the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited to the described embodiments.

[0036] Please refer to figure 1 , the present invention proposes a memory wafer testing method, comprising:

[0037] S1, connecting a wafer containing a plurality of memory chips under test through the probe card of the memory tester, so as to realize the physical and electrical connection between the memory tester and each memory chip under test on the wafer;

[0038] S2, grouping the test probes of the probe card, so as to group all the memory chips under test;

[0039] S3, using the precision measurement unit of the memory testing machine to perform a group short-circuit test on the memory chips on the wafer accor...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention provides a method for testing memory wafers and a memory testing machine. Before performing wafer needle testing such as functional testing, the testing method first performs a group short-circuit test on the same test memory chips on the wafer to determine whether the wafer is invalid. , and only after the wafer passes the short-circuit test, the memory tester is run for wafer needle testing, thereby avoiding the large leakage current of the failed wafer such as the probe card when the tester directly performs needle testing on the failed wafer In the event of damage, at the same time, bad chips can be found and removed as early as possible, reducing the average testing time of wafer testing and reducing testing costs. The memory testing machine provided by the present invention is provided with a grouping management unit, which can carry out probe grouping on the probe cards, and ground the pins of the memory chips under test in the grouping for short-circuit testing, thereby protecting the testing machine. This avoids the situation that the probe card and the like are damaged by the large leakage current of the failed wafer when the testing machine directly performs pin testing on the failed wafer.

Description

technical field [0001] The invention relates to the technical field of semiconductor testing, in particular to a memory wafer testing method and a memory testing machine. Background technique [0002] In 1947, the birth of the first transistor marked the beginning of the semiconductor industry. Since then, semiconductor production and manufacturing technology has become more and more important. Many single transistors in the past can now be interconnected and processed into a complex integrated circuit form. This is what the semiconductor industry is currently manufacturing called "very large scale" (VLSI, Very Large Scale Integration) integrated circuits, usually containing millions or even Tens of millions of gate transistors. Semiconductor circuits were originally manufactured in wafer form. A wafer is a circular silicon chip. On the basis of this semiconductor, many independent individual circuits are established. This single circuit on a wafer is called a die (that is...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/56
Inventor 任栋梁钱亮杨其燕
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products