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Semiconductor device and manufacturing method thereof

A semiconductor and device technology, applied in the field of FinFET semiconductor devices

Active Publication Date: 2015-07-01
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The formation of additional fins also increases the total w eff
Thus, width quantization is an inherent limiting factor for conventional multi-gate FinFET devices

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

Examples

Experimental program
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Effect test

Embodiment Construction

[0029] refer to figure 2 The semiconductor structure 100 includes a bulk semiconductor substrate 102 extending along an X-axis to define a height, and extending along a Y-axis perpendicular to the X-axis to define a length. The bulk semiconductor substrate 102 may be formed of a semiconductor material such as silicon (Si).

[0030] turn to image 3 , a hard mask layer 103 is formed on the upper surface of the bulk semiconductor substrate 102 . The hard mask layer 103 may be formed using chemical vapor deposition (CVD), and may be formed of a nitride mask material, as would be understood by those of ordinary skill in the art.

[0031] refer to Figure 4 , forming the core layer 104 on the upper surface of the hard mask layer 103 . The core layer 104 can be made of silicon oxide (SiO 2 ) CVD formation. Further, the core layer 104 may be formed of a material different in composition from the hard mask layer 103 to achieve etch selectivity. Materials for the core layer 104 ...

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Abstract

A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate. The first semiconductor fin extends along the second direction at a first distance to define a first fin width. A first gate channel is formed between a first source / drain junction formed in the substrate and a second source / drain junction formed in the first semiconductor fin. A first gate stack is formed on sidewalls of the first gate channel. A first spacer is interposed between the first gate stack and the first source / drain junction.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly, to FinFET semiconductor devices. Background technique [0002] Conventional multi-gate FinFET semiconductor devices include one or more semiconductor fins (fin) that run along the length (l eff ) extend to define the fin length. Fin width (w fin ) extends perpendicular to the fin length. With gate length (l GATE ) gate channel is defined between the source (S) region and the drain (D) region. Source region (S), gate channel (l GATE ) and the drain region (D) are typically formed in the same plane as each other. The current flows parallel to the l between the source (S) and drain (D) regions eff flow. To achieve higher drive currents, conventional FinFET devices may include multiple fins along the width of the FinFET device (w eff ) are formed parallel to each other, as shown in Figure 1. Therefore, as the need to drive higher currents increases, it becomes necessar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/66795H01L29/66553H01L27/0886H01L29/06H01L29/7851H01L21/823431H01L21/823412H01L21/823437H01L21/823468H01L29/1033H01L29/42376
Inventor V·S·巴斯克刘作光山下典洪叶俊呈
Owner IBM CORP
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