A method and system for reducing power consumption of multi-core terminal memory access

Abstract

The invention provides a method for reducing memory access power consumption of a multi-core terminal, and designs a corresponding device for supporting the method. The method for reducing the memory access power consumption of the multi-core terminal includes: selecting a running time window of a core in N cores as a standard window; using a multi-core synchronization module to perform alignment synchronization interrupt configuration on the residual N-1 cores, wherein N is a positive integer larger than or equal to 2; awakening the core used as the standard window so as to enable the core used as the standard window to exit from a sleep state, and simultaneously sending awakening interrupt to the residual N-1 cores, and then awakening the residual N-1 cores through the awakening interrupt; using the multi-core synchronization module to judge whether the awakening interrupt is alignment synchronization interrupt configuration of the core used as the standard window, and if yes, keeping the residual N-1 cores in an awakened state, or if not, enabling the residual N-1 cores to enter the sleep state; if keeping the residual N-1 cores in the awakened state, starting all the awakened cores to processing tasks and simultaneously access a memory; enabling the core used as the standard window to enter the awakened state after the corresponding task is completely processed, and simultaneously using the multi-core synchronization module to compel all the residual cores which do not completely process the corresponding tasks to enter the sleep state and stop accessing to the memory.

Description

Technical field [0001] The present invention relates to the field of communication technology, in particular to a method and system for reducing the power consumption of multi-core terminal memory access. Background technique [0002] In the prior art, in the operating power consumption of a multi-core (processor) terminal, the power consumption overhead of memory access occupies a relatively large proportion, and usually can reach about 20% to 30% of the power consumption of the whole machine. Memory access power consumption is mainly consumed on the memory access link, which specifically includes the internal memory controller of the chip and the external double data rate synchronous dynamic random access memory (Double Data Rate, DDR). Furthermore, memory access power consumption is determined by two factors: memory access speed and memory access time length. [0003] Please refer to figure 1 , Which is a schematic diagram of the principle of reducing memory access power consum...

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Problems solved by technology

[0006] The purpose of the present invention is to provide a method and system for reducing the memory access power consumption of a multi-core terminal, so as to solve the problem that the prior art cannot reduce the memory access time length of a multi-core system to reduce memory access power consumption

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