Eureka AIR delivers breakthrough ideas for toughest innovation challenges, trusted by R&D personnel around the world.

Method for improving breakdown voltage of gate oxide layer of groove-type VDMOS device

A gate oxide layer and oxide layer technology, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as lower breakdown voltage, lower gate oxide layer quality, and inability to perform selective etching, etc., to achieve The effect of increasing the breakdown voltage

Active Publication Date: 2015-06-03
FOUNDER MICROELECTRONICS INT
View PDF3 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Wet etching usually immerses the etching material in the etching solution for etching, which has good selectivity and isotropy, and the width of lateral etching is close to the depth of vertical etching, but the distance between adjacent rings is relatively small. It is not applicable in small cases; dry etching uses plasma for etching, which has good anisotropy, but cannot be selectively etched. In order to ensure that the initial oxide layer is etched clean, usually in dry etching overetch
[0004] These operations in the process of making the initial ring area can easily cause damage to the surface of the epitaxial layer of the silicon substrate, resulting in a decrease in the quality of the gate oxide layer grown on the damaged site, a decrease in the breakdown voltage, and ultimately the failure of the device IGSS

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for improving breakdown voltage of gate oxide layer of groove-type VDMOS device
  • Method for improving breakdown voltage of gate oxide layer of groove-type VDMOS device
  • Method for improving breakdown voltage of gate oxide layer of groove-type VDMOS device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0029] A method for improving the breakdown voltage of the gate oxide layer of the trench type VDMOS device of the present invention may comprise the steps of:

[0030] Step 1, providing a silicon substrate with an epitaxial layer;

[0031] Specific as figure 1 As shown, the silicon substrate with an epitaxial layer can be a conventional epitaxial wafer in this field, and an epitaxial layer 2 can also be grown on a silicon substrate 1 by a conventional method in this field; An N-type epitaxial layer 2 is formed on one side surface of the silicon substrate 1 .

[0032] Step 2, forming an initial oxide layer on the epitaxial layer of the silicon substrate;

[0033] Specifically, the epitaxial layer 2 of the silicon substrate 1 can be formed by wet oxidation with a thickness of The initial oxide layer 3; in this embodiment, the thickness of the formed initial oxide layer 3 can be The temperature of wet oxidation may be 950°C.

[0034] Step 3, photolithography and etching, ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a method for improving a breakdown voltage of a gate oxide layer of a groove-type VDMOS device. The method comprises the following steps of providing a silicon substrate with an epitaxial layer; forming an initial oxide layer on the epitaxial layer of the silicon substrate; photoetching and etching so as to form an active region pattern on the initial oxide layer; injecting ions, and forming an active region in the epitaxial layer below the active region pattern; photoetching, sequentially performing wet etching and dry etching, and forming a loop region pattern and a grid pattern on the initial oxide layer, wherein the initial oxide layer is reserved above the loop region pattern and the grid pattern; injecting ions, and forming a loop region in the epitaxial layer below the loop region pattern; forming a gate above the grid pattern. The method is capable of effectively protecting the surface of the epitaxial layer below the gate oxide layer from being damaged by processes such as etching and injection, thus obviously improving the breakdown voltage of the gate oxide layer and effectively improving an IGSS failure ratio.

Description

technical field [0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a method for increasing the breakdown voltage of a gate oxide layer of a trench type VDMOS device. Background technique [0002] For trench VDMOS devices, the breakdown voltage of the gate oxide layer is a very important performance parameter. If the breakdown voltage of the gate oxide layer is low, it will lead to an increase in the failure ratio of gate-source leakage (IGSS), and even lead to the scrapping of the entire device in severe cases. [0003] In the manufacturing process of the initial ring region of the trench VDMOS device, operations such as ion implantation and etching are usually required, and the etching process includes wet etching and dry etching. Wet etching usually immerses the etching material in the etching solution for etching, which has good selectivity and isotropy, and the width of lateral etching is close to the depth o...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/28
CPCH01L29/401H01L29/66712
Inventor 赵圣哲
Owner FOUNDER MICROELECTRONICS INT
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Eureka Blog
Learn More
PatSnap group products