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Task scheduling optimizing method based on SMP (symmetric multi-processing) system

A technology of task scheduling and optimization method, applied in the direction of program startup/switching, resource allocation, multi-programming device, etc., can solve the problems of long-delay bottleneck of off-chip memory access operation, decrease of bus effective utilization, etc., to achieve easy promotion, Improve the overall utilization rate and the effect of strong practicability

Active Publication Date: 2015-06-03
SHANDONG LANGCHAO YUNTOU INFORMATION TECH CO LTD
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Problems solved by technology

[0004] With the further increase in the speed gap between the processor and the main memory, the long-latency bottleneck of the off-chip memory access operation will easily lead to a decrease in the overall effective utilization of the bus in the SMP system

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  • Task scheduling optimizing method based on SMP (symmetric multi-processing) system
  • Task scheduling optimizing method based on SMP (symmetric multi-processing) system

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Embodiment Construction

[0019] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0020] With the further increase in the speed gap between the processor and the main memory, the long-delay bottleneck of off-chip memory access operations will easily lead to a decrease in the overall effective utilization of the bus in the SMP system. The invention proposes an SMP system-based task scheduling optimization method, which mainly solves the problem of system bus resource utilization in the SMP multi-core and multi-thread scenario.

[0021] The purpose of the present invention is achieved in this way, adopting the scheduling idea based on the use of process bandwidth, if the process bandwidth usage that has been counted in advance can be considered when performing process migration, the SMP system bus bandwidth can be optimized while performing load balancing usage of.

[0022] A task scheduling optimization method based on the S...

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Abstract

The invention discloses a task scheduling optimizing method based on an SMP (symmetric multi-processing) system. The task scheduling optimizing method specifically comprises the following steps of firstly, dividing the accessing types; according to the accessing intensity on a memory or a bus, dividing a to-be-scheduled thread into an accessing delay sensitive type and an accessing intensive type; accessing the thread bandwidth, namely the bus accessing rate of the thread in the running process is obtained by a built-in hardware property counting function of a processor; equalizing and optimizing a load, wherein the load is equalized by a calling function according to a scheduling domain; according to the use conditions of the bus bandwidth, dividing an SMP task scheduling optimizing strategy into two parts, namely a property technical sampling module and a bus accessing load equalizing module. Compared with the prior art, the task scheduling optimizing method based on the SMP system has the advantages that the use of the bus bandwidth is optimized on the basis of no influence on the CPU (central processing unit) load equalizing effect of the original algorithm, the effective utilization rate of the bus is improved, the practicality is high, and the method is suitable for being popularized.

Description

technical field [0001] The invention relates to a multiprocessor data scheduling technology, in particular to a highly practical task scheduling optimization method based on an SMP system. Background technique [0002] During the period from 1985 to 2000, the growth of microprocessor performance accompanied by the increase of single processor main frequency or instruction level parallelism reached the highest level since the birth of the first transistor computer in the late 1950s and early 1960s. speed. Relying on the continuous refinement and improvement of the integrated circuit manufacturing process, the integration of transistors on the processor has been continuously improved, and many technologies aimed at improving instruction-level parallelism have been added to the microprocessor. However, none of these technologies can change the thread. Serial execution mode. Instructions that can be used for parallel execution can be found from serial programs by means of inst...

Claims

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Application Information

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IPC IPC(8): G06F9/50G06F9/48
Inventor 周恒钊刘璧怡
Owner SHANDONG LANGCHAO YUNTOU INFORMATION TECH CO LTD
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