Exception handling method and structure tolerant of missing cache and capable of emptying assembly line quickly

Abstract

The invention provides an exception handling method and structure tolerant of missing cache and capable of emptying an assembly line quickly. The exception handling method includes the steps that firstly, a false hit state is defined, and the access result of the cache by invalid commands emptied by the assembly line is marked; correct command codes or data words are not guaranteed by the cache under the false hit state, and the corresponding cache information of access addresses is output directly; an assembly line emptying signal is directly acted on the command cache in the command taking operation in the false hit state to enable the false hit state to be selected when the invalid commands have access to the cache; when exception handling begins, data cache is selected and controlled through the assembly line emptying signal and the or logic of a storage access level invalid marking signal; when an exception occurs, the cache enters the false hit state to enable the assembly line to advance continuously. The invention further discloses the structure applying the exception handling method. By means of the exception handling method and structure tolerant of missing the cache and capable of emptying the assembly line quickly, the exception handling speed can be increased, and the real-time performance of the system is improved.

Description

technical field [0001] The invention relates to a structure and a method for a RISC processor of a Harvard structure to quickly clear a pipeline when performing abnormal processing, in particular to an abnormal processing method and a processing structure for quickly clearing a pipeline that tolerates a lack of cache. Background technique [0002] At present, high-performance microprocessors generally use a hierarchical multi-level cache as a buffer for data and instructions, so as to reduce the speed difference between the processor and the memory. Among them, the first-level cache has a small access delay, which is basically consistent with the speed of the processor. In order to obtain parallel access to instructions and data, it is usually divided into independent instruction cache and data cache, which is the so-called Harvard structure; The second-level cache generally stores instructions and data together, and it can be on-chip or off-chip; in future high-end designs,...

AI Technical Summary

Problems solved by technology

[0005] Aiming at the problems in the prior art, the present invention provides a method to eliminate the pipeline stall caused by the lack of cache access of invalid instructions by setting the "false hit" state in the conventional blocking cache, without adding additional complex hardware logic That is, it can quickly empty the pipeline in occasional abnormal events, thereby speeding up the speed of exception processing and improving the real-time tolerance of the computer system. The exception handling method and its processing structure of quickly emptying the pipeline due to lack of cache

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