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SOI LDMOS device with extending gate structure

A technology for extending gates and devices, applied in the field of semiconductor power devices, can solve problems such as uneven distribution of parasitic resistance and uneven temperature distribution, and achieve the effects of improving device withstand voltage, stable device operation, and uniform temperature distribution

Inactive Publication Date: 2014-12-03
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present invention aims at the technical problem that the linearly doped drift region in the existing lateral SOI LDMOS device will cause uneven distribution of parasitic resistance in the drift region, thereby resulting in uneven temperature distribution during device operation, and provides an SOI LDMOS with an extended gate structure device

Method used

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  • SOI LDMOS device with extending gate structure
  • SOI LDMOS device with extending gate structure
  • SOI LDMOS device with extending gate structure

Examples

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Embodiment 1

[0026] Figure 4a A cross-sectional view of a typical extended-gate SOI LDMOS device is given. It includes a substrate layer 1 vertically from bottom to top, a dielectric buried layer 2 and a first conductivity type semiconductor active layer 3 . One side of the first conductivity type semiconductor active layer 3 has a second conductivity type semiconductor body region 4, and the surface of the second conductivity type semiconductor body region 4 has an adjacent first conductivity type semiconductor source region 6 and a second conductivity type semiconductor body contact. Region 5, the first conductivity type semiconductor source region 6 and the second conductivity type semiconductor body contact region 5 lead out the terminal metallization source S; the other side of the first conductivity type semiconductor active layer 3 has a first conductivity type semiconductor drain Region 7, the surface of the drain region 7 of the semiconductor of the first conductivity type leads...

Embodiment 2

[0029] Figure 4b A schematic structure diagram of an extended-gate SOI LDMOS device with segmental change doping in the drift region is given. Compared with Embodiment 1, the doping concentration of the drift region 3a in the device of this embodiment increases in sections from near the body region 4 to near the drain region 7 . The sub-doped drift region will weaken the influence of the RESURF effect on the electric field distribution in the drift region in SOI devices. Therefore, compared with the device in Embodiment 1, the withstand voltage of the device in this example can be significantly improved, but since the drift region requires segmental doping, the process requirement is higher.

Embodiment 3

[0031] Figure 4c A schematic structure diagram of an extended-gate SOI LDMOS device doped with variable conductivity in the high-resistance region is given. Compared with Example 2, the device of this example adopts the doping of the second conductivity type in the part of the high resistance region 10 of the extended gate close to the gate contact region 9, and adopts the doping of the first conductivity type in the part close to the field stop region 11. Doped. The doping of the first conductivity type in the part close to the field stop region 11 can avoid damage to the drift region after the doping of the second conductivity type close to the field stop region 11 is fully depleted in the high resistance region 10 in the off-voltage withstand state of the device. Adverse effects of longitudinal electric field strength. Therefore, compared with the device in Embodiment 2, the withstand voltage of the device in this example will be improved, but because the doping type of ...

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Abstract

The invention discloses an SOI LDMOS device with an extending gate structure, and belongs to the technical field of semiconductor power devices. According to the SOI LDMOS device, the extending gate structure extending from a polysilicon gate to a drain electrode is introduced into the surface of a drift region of a conventional SOI LDMOS device. A PN junction which is reversely biased when the device is in the on state is introduced into the extending gate structure to reduce a leakage current. The extending gate structure is characterized in that on one hand, when the device is in the on state, a majority carrier accumulation layer is sensed on the portion, close to extending gate media, of the surface of the drift region, an ultralow resistance channel is provided for the on-state current, the specific on resistance of the device is accordingly and remarkably reduced, and the specific on resistance does not depend on the doping concentration of the drift region; on the other hand, when the device is in the off state, distribution of an electric field in the drift region is adjusted through the extending gate structure, and the voltage resistance of the device is accordingly improved. In addition, the vast majority of the on-state current flows through the low-resistance channel of the charge accumulation layer, temperature distribution of the SOI LDMOS device is accordingly even, and the SOI LDMOS device is stable.

Description

technical field [0001] The invention belongs to the technical field of semiconductor power devices, and relates to a lateral semiconductor power device, in particular to a high-voltage, low-resistance lateral power SOI LDMOS (Lateral Double-diffused Metal-Oxide-Semiconductor, lateral double-diffused metal-oxide- Semiconductor device. Background technique [0002] The key parameters of a power MOSFET are high voltage and low on-resistance. Since the MOSFET is a unipolar device, the increase in its withstand voltage is accompanied by an increase in the length of the drift region and a decrease in the concentration of the drift region; moreover, for traditional high-voltage power MOSFETs, its on-resistance is mainly determined by its resistance in the drift region. This results in a device specific on-resistance R on,sp (Specific on-resistance = on-resistance × device area) relative to the withstand voltage BV according to the relationship R on,sp ∝BV 2.5 A sharp increase, ...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/423H01L29/06
CPCH01L29/4238H01L29/7824H01L29/783H01L29/7818H01L29/402H01L29/0878
Inventor 罗小蓉李鹏程田瑞超徐青张彦辉魏杰石先龙张波
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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