LDO (low dropout regulator) provided with slope starting circuit

Abstract

The invention provides an LDO (low dropout regulator) provided with a slope starting circuit. The regulator comprises the starting circuit (201) and a main regulator circuit (202), wherein on one hand, the starting circuit (201) is used for generating two channels of slope enabling signals EN and EN_b to serve as input signals at an enabling end of the main regulator circuit, on the other hand, the starting circuit is used for outputting a voltage signal Vro to serve as input of the main regulator circuit, and the voltage signal Vro rises in a slope manner and is finally stabilized at certain voltage value; the main regulator circuit (202) is used for proportionally amplifying the voltage signal Vro and outputting stable voltage Vo under the control of the two channels of slope enabling signals EN and EN_b. The LDO can effectively prevent surge current during power-up starting and consumes quite little current.

Description

technical field [0001] The invention belongs to the technical field of low-dropout linear regulators (LDOs), and in particular relates to an LDO with a ramp start circuit. Background technique [0002] In recent years, with the rapid development of industries such as communications, computers, and consumer electronics, people's demand for electronic products is increasing, which also drives the development of related integrated circuit chip industries. In electronic products, especially in portable electronic products such as mobile phones, digital cameras, and handheld computers, in order to improve power efficiency and extend battery life, power management chips are often required to regulate the voltage provided by the battery; The performance impact is huge. LDO is a power management device that can provide stable voltage and has high energy efficiency, and has a wide range of applications in many occasions. [0003] figure 1 (a) is a common LDO structure diagram, con...

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Problems solved by technology

[0006] However, these methods have disadvantages. The first method will increase the cost and volume of electronic products because of the use of a large number of off-chip components; the second method only ensures that there is no surge current after the EN signal is valid. , but when VDD is powered on, there may still be a surge current; because when VDD is powered on very fast (such as on the order of hundreds of nanoseconds), M p The gate voltage rises slower than the source voltage, which will make the LDO flow a large pulse current, such as image 3 as shown in (b)

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