A kind of SRAM memory and preparation method thereof

Abstract

The invention relates to an SRAM memory and a preparation method thereof, the method comprising: providing a semiconductor substrate; performing halo / LDD ion implantation on a pull-down transistor on the semiconductor substrate; and performing halo / LDD ion implantation on the pull-up transistor on the semiconductor substrate performing halo / LDD ion implantation; performing halo / LDD ion implantation on the PMOS region of the core region on the semiconductor substrate; performing halo / LDD ion implantation on the NMOS region of the core region on the semiconductor substrate; performing halo / LDD ion implantation on the PMOS area of ​​the input-output area on the semiconductor substrate; performing halo / LDD ion implantation on the NMOS area of ​​the input-output area on the semiconductor substrate. The method of the present invention changes the conventional ion implantation sequence in the prior art. After the gate structure is formed in the SRAM device, the gate etching damage is repaired, and then the step of PD halo / LDD ion implantation is performed immediately. The PD device has experienced the least The ashing and wet stripping process of photoresist minimizes the PD threshold voltage mismatch, which can effectively improve the yield of SRAM.

Description

technical field [0001] The invention relates to the field of semiconductors, and in particular, the invention relates to an SRAM memory and a preparation method thereof. Background technique [0002] Static random access memory (SRAM), as a member of volatile memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, multimedia players ) and other fields. In particular, high-speed synchronous SRAMs are used in applications such as workstations with cache memory, which provides high-speed storage for reused data or instructions. [0003] In the design and production process of SRAM devices, due to uncertainties, random errors, gradient errors and other reasons, some semiconductor devices that are identical in design have errors after production, which is called the mismatch process of semiconductor devices (Mismatch process)....

AI Technical Summary

Problems solved by technology

[0007] At present, the LDD of the SRAM pull-down transistor (Pull Down, PD) is after the process of forming the gate structure, and also after the injection of the PU (Pull Up, PU) LDD, which leads to a decrease in device performance. Therefore, to improve the performance of semiconductor devices, It is necessary to improve the preparation process of the current device

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